[PATCH AUTOSEL for 4.9 071/293] x86/mce: Don't disable MCA banks when offlining a CPU on AMD

[Sasha Levin]

From: Yazen Ghannam 

[ Upstream commit ec33838244c8535b23b8d24b167996fd1318bb68 ]

AMD systems have non-core, shared MCA banks within a die. These banks
are controlled by a master CPU per die. If this CPU is offlined then all
the shared banks are disabled in addition to the CPU's core banks.

Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
between SMT thread siblings. If a CPU is offlined then all its sibling's
MCA banks are also disabled.

Extend the existing vendor check to AMD too.

Signed-off-by: Yazen Ghannam 
[ Fix up comment. ]
Signed-off-by: Borislav Petkov 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170613162835.30750-8...@alien8.de
Signed-off-by: Ingo Molnar 
Signed-off-by: Sasha Levin 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7bbd50fa72ad..0a8ba9adb04a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -2187,12 +2187,13 @@ static void mce_disable_error_reporting(void)
 static void vendor_disable_error_reporting(void)
 {
/*
-* Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
+* Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
 * Disabling them for just a single offlined CPU is bad, since it will
 * inhibit reporting for all shared resources on the socket like the
 * last level cache (LLC), the integrated memory controller (iMC), etc.
 */
-   if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+   if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
+   boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
return;
 
mce_disable_error_reporting();
-- 
2.15.1

[PATCH AUTOSEL for 4.9 071/293] x86/mce: Don't disable MCA banks when offlining a CPU on AMD

[Sasha Levin]

From: Yazen Ghannam 

[ Upstream commit ec33838244c8535b23b8d24b167996fd1318bb68 ]

AMD systems have non-core, shared MCA banks within a die. These banks
are controlled by a master CPU per die. If this CPU is offlined then all
the shared banks are disabled in addition to the CPU's core banks.

Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
between SMT thread siblings. If a CPU is offlined then all its sibling's
MCA banks are also disabled.

Extend the existing vendor check to AMD too.

Signed-off-by: Yazen Ghannam 
[ Fix up comment. ]
Signed-off-by: Borislav Petkov 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170613162835.30750-8...@alien8.de
Signed-off-by: Ingo Molnar 
Signed-off-by: Sasha Levin 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7bbd50fa72ad..0a8ba9adb04a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -2187,12 +2187,13 @@ static void mce_disable_error_reporting(void)
 static void vendor_disable_error_reporting(void)
 {
/*
-* Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
+* Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
 * Disabling them for just a single offlined CPU is bad, since it will
 * inhibit reporting for all shared resources on the socket like the
 * last level cache (LLC), the integrated memory controller (iMC), etc.
 */
-   if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+   if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
+   boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
return;
 
mce_disable_error_reporting();
-- 
2.15.1