On 8/14/2017 11:02 PM, Paolo Bonzini wrote:
On 14/08/2017 16:32, Yu Zhang wrote:
On 8/14/2017 10:13 PM, Paolo Bonzini wrote:
On 14/08/2017 13:37, Yu Zhang wrote:
Thanks a lot for your comments, Paolo. :-)
On 8/14/2017 3:31 PM, Paolo Bonzini wrote:
On 12/08/2017 15:35, Yu Zhang wrote:
On 14/08/2017 16:32, Yu Zhang wrote:
>
>
> On 8/14/2017 10:13 PM, Paolo Bonzini wrote:
>> On 14/08/2017 13:37, Yu Zhang wrote:
>>> Thanks a lot for your comments, Paolo. :-)
>>>
>>>
>>> On 8/14/2017 3:31 PM, Paolo Bonzini wrote:
On 12/08/2017 15:35, Yu Zhang wrote:
>struct rsvd_bits_
On 8/14/2017 10:13 PM, Paolo Bonzini wrote:
On 14/08/2017 13:37, Yu Zhang wrote:
Thanks a lot for your comments, Paolo. :-)
On 8/14/2017 3:31 PM, Paolo Bonzini wrote:
On 12/08/2017 15:35, Yu Zhang wrote:
struct rsvd_bits_validate {
-u64 rsvd_bits_mask[2][4];
+u64 rsvd_bits_mask[
On 14/08/2017 13:37, Yu Zhang wrote:
> Thanks a lot for your comments, Paolo. :-)
>
>
> On 8/14/2017 3:31 PM, Paolo Bonzini wrote:
>> On 12/08/2017 15:35, Yu Zhang wrote:
>>> struct rsvd_bits_validate {
>>> -u64 rsvd_bits_mask[2][4];
>>> +u64 rsvd_bits_mask[2][5];
>>> u64 bad_mt_x
Thanks a lot for your comments, Paolo. :-)
On 8/14/2017 3:31 PM, Paolo Bonzini wrote:
On 12/08/2017 15:35, Yu Zhang wrote:
struct rsvd_bits_validate {
- u64 rsvd_bits_mask[2][4];
+ u64 rsvd_bits_mask[2][5];
u64 bad_mt_xwr;
};
Can you change this 4 to PT64_ROOT_MAX_LEV
On 12/08/2017 15:35, Yu Zhang wrote:
> struct rsvd_bits_validate {
> - u64 rsvd_bits_mask[2][4];
> + u64 rsvd_bits_mask[2][5];
> u64 bad_mt_xwr;
> };
Can you change this 4 to PT64_ROOT_MAX_LEVEL in patch 2?
> - if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL &&
> -
Extends the shadow paging code, so that 5 level shadow page
table can be constructed if VM is running in 5 level paging
mode.
Also extends the ept code, so that 5 level ept table can be
constructed if maxphysaddr of VM exceeds 48 bits. Unlike the
shadow logic, KVM should still use 4 level ept tabl
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