[PATCH v1 4/5] clk: mediatek: add clk support for MT6755
Add MT6755 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks Signed-off-by: Mars Cheng--- drivers/clk/mediatek/Kconfig | 32 ++ drivers/clk/mediatek/Makefile |5 + drivers/clk/mediatek/clk-mt6755-img.c | 81 drivers/clk/mediatek/clk-mt6755-mm.c | 148 +++ drivers/clk/mediatek/clk-mt6755-vdec.c | 91 + drivers/clk/mediatek/clk-mt6755-venc.c | 78 drivers/clk/mediatek/clk-mt6755.c | 666 7 files changed, 1101 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6755-img.c create mode 100644 drivers/clk/mediatek/clk-mt6755-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6755-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt6755-venc.c create mode 100644 drivers/clk/mediatek/clk-mt6755.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 28739a9..1cc7061 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -50,6 +50,38 @@ config COMMON_CLK_MT2701_BDPSYS ---help--- This driver supports Mediatek MT2701 bdpsys clocks. +config COMMON_CLK_MT6755 + bool "Clock driver for Mediatek MT6755" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM64 + ---help--- + This driver supports Mediatek MT6755 basic clocks. + +config COMMON_CLK_MT6755_MMSYS + bool "Clock driver for Mediatek MT6755 mmsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 mmsys clocks. + +config COMMON_CLK_MT6755_IMGSYS + bool "Clock driver for Mediatek MT6755 imgsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 imgsys clocks. + +config COMMON_CLK_MT6755_VDECSYS + bool "Clock driver for Mediatek MT6755 vdecsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 vdecsys clocks. + +config COMMON_CLK_MT6755_VENCSYS + bool "Clock driver for Mediatek MT6755 vencsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 vencsys clocks. + config COMMON_CLK_MT6797 bool "Clock driver for Mediatek MT6797" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 2a755b5..ed680fc 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,5 +1,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o +obj-$(CONFIG_COMMON_CLK_MT6755) += clk-mt6755.o +obj-$(CONFIG_COMMON_CLK_MT6755_IMGSYS) += clk-mt6755-img.o +obj-$(CONFIG_COMMON_CLK_MT6755_MMSYS) += clk-mt6755-mm.o +obj-$(CONFIG_COMMON_CLK_MT6755_VDECSYS) += clk-mt6755-vdec.o +obj-$(CONFIG_COMMON_CLK_MT6755_VENCSYS) += clk-mt6755-venc.o obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o diff --git a/drivers/clk/mediatek/clk-mt6755-img.c b/drivers/clk/mediatek/clk-mt6755-img.c new file mode 100644 index 000..b9e6832 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6755-img.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Wendell Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x0004, + .clr_ofs = 0x0008, + .sta_ofs = 0x, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = _cg_regs, \ + .shift = _shift,\ + .ops = _clk_gate_ops_setclr,\ + } + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_IMAGE_LARB2_SMI, "img_image_larb2_smi", "mm_sel", 0), + GATE_IMG(CLK_IMG_IMAGE_CAM_SMI, "img_image_cam_smi", "mm_sel", 5), + GATE_IMG(CLK_IMG_IMAGE_CAM_CAM, "img_image_cam_cam", "mm_sel", 6), + GATE_IMG(CLK_IMG_IMAGE_SEN_TG, "img_image_sen_tg", "mm_sel", 7), +
[PATCH v1 4/5] clk: mediatek: add clk support for MT6755
Add MT6755 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks Signed-off-by: Mars Cheng --- drivers/clk/mediatek/Kconfig | 32 ++ drivers/clk/mediatek/Makefile |5 + drivers/clk/mediatek/clk-mt6755-img.c | 81 drivers/clk/mediatek/clk-mt6755-mm.c | 148 +++ drivers/clk/mediatek/clk-mt6755-vdec.c | 91 + drivers/clk/mediatek/clk-mt6755-venc.c | 78 drivers/clk/mediatek/clk-mt6755.c | 666 7 files changed, 1101 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6755-img.c create mode 100644 drivers/clk/mediatek/clk-mt6755-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6755-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt6755-venc.c create mode 100644 drivers/clk/mediatek/clk-mt6755.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 28739a9..1cc7061 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -50,6 +50,38 @@ config COMMON_CLK_MT2701_BDPSYS ---help--- This driver supports Mediatek MT2701 bdpsys clocks. +config COMMON_CLK_MT6755 + bool "Clock driver for Mediatek MT6755" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM64 + ---help--- + This driver supports Mediatek MT6755 basic clocks. + +config COMMON_CLK_MT6755_MMSYS + bool "Clock driver for Mediatek MT6755 mmsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 mmsys clocks. + +config COMMON_CLK_MT6755_IMGSYS + bool "Clock driver for Mediatek MT6755 imgsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 imgsys clocks. + +config COMMON_CLK_MT6755_VDECSYS + bool "Clock driver for Mediatek MT6755 vdecsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 vdecsys clocks. + +config COMMON_CLK_MT6755_VENCSYS + bool "Clock driver for Mediatek MT6755 vencsys" + depends on COMMON_CLK_MT6755 + ---help--- + This driver supports Mediatek MT6755 vencsys clocks. + config COMMON_CLK_MT6797 bool "Clock driver for Mediatek MT6797" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 2a755b5..ed680fc 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,5 +1,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o obj-$(CONFIG_RESET_CONTROLLER) += reset.o +obj-$(CONFIG_COMMON_CLK_MT6755) += clk-mt6755.o +obj-$(CONFIG_COMMON_CLK_MT6755_IMGSYS) += clk-mt6755-img.o +obj-$(CONFIG_COMMON_CLK_MT6755_MMSYS) += clk-mt6755-mm.o +obj-$(CONFIG_COMMON_CLK_MT6755_VDECSYS) += clk-mt6755-vdec.o +obj-$(CONFIG_COMMON_CLK_MT6755_VENCSYS) += clk-mt6755-venc.o obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o diff --git a/drivers/clk/mediatek/clk-mt6755-img.c b/drivers/clk/mediatek/clk-mt6755-img.c new file mode 100644 index 000..b9e6832 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6755-img.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Wendell Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x0004, + .clr_ofs = 0x0008, + .sta_ofs = 0x, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) {\ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = _cg_regs, \ + .shift = _shift,\ + .ops = _clk_gate_ops_setclr,\ + } + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_IMAGE_LARB2_SMI, "img_image_larb2_smi", "mm_sel", 0), + GATE_IMG(CLK_IMG_IMAGE_CAM_SMI, "img_image_cam_smi", "mm_sel", 5), + GATE_IMG(CLK_IMG_IMAGE_CAM_CAM, "img_image_cam_cam", "mm_sel", 6), + GATE_IMG(CLK_IMG_IMAGE_SEN_TG, "img_image_sen_tg", "mm_sel", 7), + GATE_IMG(CLK_IMG_IMAGE_SEN_CAM, "img_image_sen_cam", "camtg_sel", 8), +