Re: [PATCH v2] arm64: dts: msm8916: Add cpu cooling maps

2018-03-07 Thread Viresh Kumar 
On 07-03-18, 16:56, Amit Kucheria wrote:
> On Wed, Mar 7, 2018 at 10:44 AM, Viresh Kumar  wrote:
> > On Wed, Mar 7, 2018 at 10:30 AM, Amit Kucheria  
> > wrote:
> >> From: Rajendra Nayak 
> >>
> >> Add cpu cooling maps for cpu passive trip points. The cpu cooling
> >> device states are mapped to cpufreq based scaling frequencies.
> >>
> >> Signed-off-by: Rajendra Nayak 
> >> Signed-off-by: Amit Kucheria 
> >> ---
> >>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 +++
> >>  1 file changed, 19 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
> >> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> >> index e468277..66b318e 100644
> >> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> >> @@ -15,6 +15,7 @@
> >>  #include 
> >>  #include 
> >>  #include 
> >> +#include 
> >>
> >>  / {
> >> model = "Qualcomm Technologies, Inc. MSM8916";
> >> @@ -115,6 +116,7 @@
> >> cpu-idle-states = <&CPU_SPC>;
> >> clocks = <&apcs 0>;
> >> operating-points-v2 = <&cpu_opp_table>;
> >> +   #cooling-cells = <2>;
> >
> > LGTM.
> 
> Can I take that as a Reviewed-by?

Sure.

Reviewed-by: Viresh Kumar 

-- 
viresh

Re: [PATCH v2] arm64: dts: msm8916: Add cpu cooling maps

2018-03-07 Thread Amit Kucheria 
On Wed, Mar 7, 2018 at 10:44 AM, Viresh Kumar  wrote:
> On Wed, Mar 7, 2018 at 10:30 AM, Amit Kucheria  
> wrote:
>> From: Rajendra Nayak 
>>
>> Add cpu cooling maps for cpu passive trip points. The cpu cooling
>> device states are mapped to cpufreq based scaling frequencies.
>>
>> Signed-off-by: Rajendra Nayak 
>> Signed-off-by: Amit Kucheria 
>> ---
>>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 +++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> index e468277..66b318e 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> @@ -15,6 +15,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  / {
>> model = "Qualcomm Technologies, Inc. MSM8916";
>> @@ -115,6 +116,7 @@
>> cpu-idle-states = <&CPU_SPC>;
>> clocks = <&apcs 0>;
>> operating-points-v2 = <&cpu_opp_table>;
>> +   #cooling-cells = <2>;
>
> LGTM.

Can I take that as a Reviewed-by?

Re: [PATCH v2] arm64: dts: msm8916: Add cpu cooling maps

2018-03-06 Thread Viresh Kumar 
On Wed, Mar 7, 2018 at 10:30 AM, Amit Kucheria  wrote:
> From: Rajendra Nayak 
>
> Add cpu cooling maps for cpu passive trip points. The cpu cooling
> device states are mapped to cpufreq based scaling frequencies.
>
> Signed-off-by: Rajendra Nayak 
> Signed-off-by: Amit Kucheria 
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index e468277..66b318e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  / {
> model = "Qualcomm Technologies, Inc. MSM8916";
> @@ -115,6 +116,7 @@
> cpu-idle-states = <&CPU_SPC>;
> clocks = <&apcs 0>;
> operating-points-v2 = <&cpu_opp_table>;
> +   #cooling-cells = <2>;

LGTM.

[PATCH v2] arm64: dts: msm8916: Add cpu cooling maps

2018-03-06 Thread Amit Kucheria 
From: Rajendra Nayak 

Add cpu cooling maps for cpu passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.

Signed-off-by: Rajendra Nayak 
Signed-off-by: Amit Kucheria 
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e468277..66b318e 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
model = "Qualcomm Technologies, Inc. MSM8916";
@@ -115,6 +116,7 @@
cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>;
+   #cooling-cells = <2>;
};
 
CPU1: cpu@1 {
@@ -126,6 +128,7 @@
cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>;
+   #cooling-cells = <2>;
};
 
CPU2: cpu@2 {
@@ -137,6 +140,7 @@
cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>;
+   #cooling-cells = <2>;
};
 
CPU3: cpu@3 {
@@ -148,6 +152,7 @@
cpu-idle-states = <&CPU_SPC>;
clocks = <&apcs 0>;
operating-points-v2 = <&cpu_opp_table>;
+   #cooling-cells = <2>;
};
 
L2_0: l2-cache {
@@ -196,6 +201,13 @@
type = "critical";
};
};
+
+   cooling-maps {
+   map0 {
+   trip = <&cpu_alert0>;
+   cooling-device = <&CPU0 
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   };
};
 
cpu-thermal1 {
@@ -216,6 +228,13 @@
type = "critical";
};
};
+
+   cooling-maps {
+   map0 {
+   trip = <&cpu_alert1>;
+   cooling-device = <&CPU0 
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   };
};
 
};
-- 
2.7.4