subject:"\[PATCH v2 06\/10\] video\: add support of STM32 MIPI DSI controller driver"

Re: [PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-13 Thread Patrice CHOTARD

Hi yannick

On 03/02/2018 04:44 PM, yannick fertre wrote:
> Add the STM32 DSI controller driver that uses the Synopsys DesignWare
> MIPI DSI host controller bridge.
> 
> Signed-off-by: yannick fertre 
> ---
>   drivers/video/stm32/Kconfig |  10 +
>   drivers/video/stm32/Makefile|   1 +
>   drivers/video/stm32/stm32_dsi.c | 427 
> 
>   3 files changed, 438 insertions(+)
>   create mode 100644 drivers/video/stm32/stm32_dsi.c
> 
> diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
> index 113a2bb..2ea6f18 100644
> --- a/drivers/video/stm32/Kconfig
> +++ b/drivers/video/stm32/Kconfig
> @@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
> DSI. This option enables these supports which can be used on
> devices which have RGB TFT or DSI display connected.
>   
> +config VIDEO_STM32_DSI
> + bool "Enable STM32 DSI video support"
> + depends on VIDEO_STM32
> + select VIDEO_MIPI_DSI
> + select VIDEO_BRIDGE
> + select VIDEO_DW_MIPI_DSI
> + help
> +   This option enables support DSI internal bridge which can be used on
> +   devices which have DSI display connected.
> +
>   config VIDEO_STM32_MAX_XRES
>   int "Maximum horizontal resolution (for memory allocation purposes)"
>   depends on VIDEO_STM32
> diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
> index 372a2e1..f8c3ff7 100644
> --- a/drivers/video/stm32/Makefile
> +++ b/drivers/video/stm32/Makefile
> @@ -8,3 +8,4 @@
>   #
>   
>   obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
> +obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
> diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
> new file mode 100644
> index 000..3e26433
> --- /dev/null
> +++ b/drivers/video/stm32/stm32_dsi.c
> @@ -0,0 +1,427 @@
> +/*
> + * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
> + * Author(s): Philippe Cornu  for STMicroelectronics.
> + * Yannick Fertre  for STMicroelectronics.
> + *
> + * This driver is based on the mipi dsi driver from
> + * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define HWVER_1300x31333000  /* IP version 1.30 */
> +#define HWVER_1310x31333100  /* IP version 1.31 */
> +
> +/* DSI digital registers & bit definitions */
> +#define DSI_VERSION  0x00
> +#define VERSION  GENMASK(31, 8)
> +
> +/*
> + * DSI wrapper registers & bit definitions
> + * Note: registers are named as in the Reference Manual
> + */
> +#define DSI_WCFGR0x0400  /* Wrapper ConFiGuration Reg */
> +#define WCFGR_DSIM   BIT(0)  /* DSI Mode */
> +#define WCFGR_COLMUX GENMASK(3, 1)   /* COLor MUltipleXing */
> +
> +#define DSI_WCR  0x0404  /* Wrapper Control Reg */
> +#define WCR_DSIENBIT(3)  /* DSI ENable */
> +
> +#define DSI_WISR 0x040C  /* Wrapper Interrupt and Status Reg */
> +#define WISR_PLLLS   BIT(8)  /* PLL Lock Status */
> +#define WISR_RRS BIT(12) /* Regulator Ready Status */
> +
> +#define DSI_WPCR00x0418  /* Wrapper Phy Conf Reg 0 */
> +#define WPCR0_UIX4   GENMASK(5, 0)   /* Unit Interval X 4 */
> +#define WPCR0_TDDL   BIT(16) /* Turn Disable Data Lanes */
> +
> +#define DSI_WRPCR0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
> +#define WRPCR_PLLEN  BIT(0)  /* PLL ENable */
> +#define WRPCR_NDIV   GENMASK(8, 2)   /* pll loop DIVision Factor */
> +#define WRPCR_IDFGENMASK(14, 11) /* pll Input Division Factor */
> +#define WRPCR_ODFGENMASK(17, 16) /* pll Output Division Factor */
> +#define WRPCR_REGEN  BIT(24) /* REGulator ENable */
> +#define WRPCR_BGREN  BIT(28) /* BandGap Reference ENable */
> +#define IDF_MIN  1
> +#define IDF_MAX  7
> +#define NDIV_MIN 10
> +#define NDIV_MAX 125
> +#define ODF_MIN  1
> +#define ODF_MAX  8
> +
> +/* dsi color format coding according to the datasheet */
> +enum dsi_color {
> + DSI_RGB565_CONF1,
> + DSI_RGB565_CONF2,
> + DSI_RGB565_CONF3,
> + DSI_RGB666_CONF1,
> + DSI_RGB666_CONF2,
> + DSI_RGB888,
> +};
> +
> +#define LANE_MIN_KBPS31250
> +#define LANE_MAX_KBPS50
> +
> +/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
> +#define TIMEOUT_US   20
> +
> +struct stm32_dsi_priv {
> + struct mipi_dsi_device device;
> + void __iomem *base;
> + struct udevice *panel;
> + u32 pllref_clk;
> + u32 hw_version;
> + int lane_min_kbps;
> + int lane_max_kbps;
> +};
> +
>

Re: [PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-13 Thread Patrice CHOTARD

Hi yannick

On 03/02/2018 04:44 PM, yannick fertre wrote:
> Add the STM32 DSI controller driver that uses the Synopsys DesignWare
> MIPI DSI host controller bridge.
> 
> Signed-off-by: yannick fertre 
> ---
>   drivers/video/stm32/Kconfig |  10 +
>   drivers/video/stm32/Makefile|   1 +
>   drivers/video/stm32/stm32_dsi.c | 427 
> 
>   3 files changed, 438 insertions(+)
>   create mode 100644 drivers/video/stm32/stm32_dsi.c
> 
> diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
> index 113a2bb..2ea6f18 100644
> --- a/drivers/video/stm32/Kconfig
> +++ b/drivers/video/stm32/Kconfig
> @@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
> DSI. This option enables these supports which can be used on
> devices which have RGB TFT or DSI display connected.
>   
> +config VIDEO_STM32_DSI
> + bool "Enable STM32 DSI video support"
> + depends on VIDEO_STM32
> + select VIDEO_MIPI_DSI
> + select VIDEO_BRIDGE
> + select VIDEO_DW_MIPI_DSI
> + help
> +   This option enables support DSI internal bridge which can be used on
> +   devices which have DSI display connected.
> +
>   config VIDEO_STM32_MAX_XRES
>   int "Maximum horizontal resolution (for memory allocation purposes)"
>   depends on VIDEO_STM32
> diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
> index 372a2e1..f8c3ff7 100644
> --- a/drivers/video/stm32/Makefile
> +++ b/drivers/video/stm32/Makefile
> @@ -8,3 +8,4 @@
>   #
>   
>   obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
> +obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
> diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
> new file mode 100644
> index 000..3e26433
> --- /dev/null
> +++ b/drivers/video/stm32/stm32_dsi.c
> @@ -0,0 +1,427 @@
> +/*
> + * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
> + * Author(s): Philippe Cornu  for STMicroelectronics.
> + * Yannick Fertre  for STMicroelectronics.
> + *
> + * This driver is based on the mipi dsi driver from
> + * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define HWVER_1300x31333000  /* IP version 1.30 */
> +#define HWVER_1310x31333100  /* IP version 1.31 */
> +
> +/* DSI digital registers & bit definitions */
> +#define DSI_VERSION  0x00
> +#define VERSION  GENMASK(31, 8)
> +
> +/*
> + * DSI wrapper registers & bit definitions
> + * Note: registers are named as in the Reference Manual
> + */
> +#define DSI_WCFGR0x0400  /* Wrapper ConFiGuration Reg */
> +#define WCFGR_DSIM   BIT(0)  /* DSI Mode */
> +#define WCFGR_COLMUX GENMASK(3, 1)   /* COLor MUltipleXing */
> +
> +#define DSI_WCR  0x0404  /* Wrapper Control Reg */
> +#define WCR_DSIENBIT(3)  /* DSI ENable */
> +
> +#define DSI_WISR 0x040C  /* Wrapper Interrupt and Status Reg */
> +#define WISR_PLLLS   BIT(8)  /* PLL Lock Status */
> +#define WISR_RRS BIT(12) /* Regulator Ready Status */
> +
> +#define DSI_WPCR00x0418  /* Wrapper Phy Conf Reg 0 */
> +#define WPCR0_UIX4   GENMASK(5, 0)   /* Unit Interval X 4 */
> +#define WPCR0_TDDL   BIT(16) /* Turn Disable Data Lanes */
> +
> +#define DSI_WRPCR0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
> +#define WRPCR_PLLEN  BIT(0)  /* PLL ENable */
> +#define WRPCR_NDIV   GENMASK(8, 2)   /* pll loop DIVision Factor */
> +#define WRPCR_IDFGENMASK(14, 11) /* pll Input Division Factor */
> +#define WRPCR_ODFGENMASK(17, 16) /* pll Output Division Factor */
> +#define WRPCR_REGEN  BIT(24) /* REGulator ENable */
> +#define WRPCR_BGREN  BIT(28) /* BandGap Reference ENable */
> +#define IDF_MIN  1
> +#define IDF_MAX  7
> +#define NDIV_MIN 10
> +#define NDIV_MAX 125
> +#define ODF_MIN  1
> +#define ODF_MAX  8
> +
> +/* dsi color format coding according to the datasheet */
> +enum dsi_color {
> + DSI_RGB565_CONF1,
> + DSI_RGB565_CONF2,
> + DSI_RGB565_CONF3,
> + DSI_RGB666_CONF1,
> + DSI_RGB666_CONF2,
> + DSI_RGB888,
> +};
> +
> +#define LANE_MIN_KBPS31250
> +#define LANE_MAX_KBPS50
> +
> +/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
> +#define TIMEOUT_US   20
> +
> +struct stm32_dsi_priv {
> + struct mipi_dsi_device device;
> + void __iomem *base;
> + struct udevice *panel;
> + u32 pllref_clk;
> + u32 hw_version;
> + int lane_min_kbps;
> + int lane_max_kbps;
> +};
> +
> +static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-02 Thread yannick fertre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 427 
 3 files changed, 438 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..3e26433
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-02 Thread yannick fertre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 427 
 3 files changed, 438 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..3e26433
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
+{
+

Re: [PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

Re: [PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

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