[PATCH v2 08/12] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623

[sean.wang]

From: Ryder Lee 

Modify audio related nodes to reflect the actual usage in binding documents.

Signed-off-by: Ryder Lee 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt2701.dtsi | 188 -
 arch/arm/boot/dts/mt7623.dtsi | 190 --
 2 files changed, 182 insertions(+), 196 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index cf1c8eb..180377e 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -419,104 +419,96 @@
status = "disabled";
};
 
-   afe: audio-controller@1122 {
-   compatible = "mediatek,mt2701-audio";
-   reg = <0 0x1122 0 0x2000>,
- <0 0x112a 0 0x2>;
-   interrupts =  ,
- ;
-   interrupt-names = "afe", "asys";
-   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
-
-   clocks = < CLK_INFRA_AUDIO>,
-< CLK_TOP_AUD_MUX1_SEL>,
-< CLK_TOP_AUD_MUX2_SEL>,
-< CLK_TOP_AUD_MUX1_DIV>,
-< CLK_TOP_AUD_MUX2_DIV>,
-< CLK_TOP_AUD_48K_TIMING>,
-< CLK_TOP_AUD_44K_TIMING>,
-< CLK_TOP_AUDPLL_MUX_SEL>,
-< CLK_TOP_APLL_SEL>,
-< CLK_TOP_AUD1PLL_98M>,
-< CLK_TOP_AUD2PLL_90M>,
-< CLK_TOP_HADDS2PLL_98M>,
-< CLK_TOP_HADDS2PLL_294M>,
-< CLK_TOP_AUDPLL>,
-< CLK_TOP_AUDPLL_D4>,
-< CLK_TOP_AUDPLL_D8>,
-< CLK_TOP_AUDPLL_D16>,
-< CLK_TOP_AUDPLL_D24>,
-< CLK_TOP_AUDINTBUS_SEL>,
-<>,
-< CLK_TOP_SYSPLL1_D4>,
-< CLK_TOP_AUD_K1_SRC_SEL>,
-< CLK_TOP_AUD_K2_SRC_SEL>,
-< CLK_TOP_AUD_K3_SRC_SEL>,
-< CLK_TOP_AUD_K4_SRC_SEL>,
-< CLK_TOP_AUD_K5_SRC_SEL>,
-< CLK_TOP_AUD_K6_SRC_SEL>,
-< CLK_TOP_AUD_K1_SRC_DIV>,
-< CLK_TOP_AUD_K2_SRC_DIV>,
-< CLK_TOP_AUD_K3_SRC_DIV>,
-< CLK_TOP_AUD_K4_SRC_DIV>,
-< CLK_TOP_AUD_K5_SRC_DIV>,
-< CLK_TOP_AUD_K6_SRC_DIV>,
-< CLK_TOP_AUD_I2S1_MCLK>,
-< CLK_TOP_AUD_I2S2_MCLK>,
-< CLK_TOP_AUD_I2S3_MCLK>,
-< CLK_TOP_AUD_I2S4_MCLK>,
-< CLK_TOP_AUD_I2S5_MCLK>,
-< CLK_TOP_AUD_I2S6_MCLK>,
-< CLK_TOP_ASM_M_SEL>,
-< CLK_TOP_ASM_H_SEL>,
-< CLK_TOP_UNIVPLL2_D4>,
-< CLK_TOP_UNIVPLL2_D2>,
-< CLK_TOP_SYSPLL_D5>;
-
-   clock-names = "infra_sys_audio_clk",
-"top_audio_mux1_sel",
-"top_audio_mux2_sel",
-"top_audio_mux1_div",
-"top_audio_mux2_div",
-"top_audio_48k_timing",
-"top_audio_44k_timing",
-"top_audpll_mux_sel",
-"top_apll_sel",
-"top_aud1_pll_98M",
-"top_aud2_pll_90M",
-"top_hadds2_pll_98M",
-"top_hadds2_pll_294M",
-"top_audpll",
-"top_audpll_d4",
-"top_audpll_d8",
-"top_audpll_d16",
-"top_audpll_d24",
-"top_audintbus_sel",
-"clk_26m",
-"top_syspll1_d4",
-"top_aud_k1_src_sel",
-"top_aud_k2_src_sel",
-"top_aud_k3_src_sel",
-"top_aud_k4_src_sel",
-"top_aud_k5_src_sel",
-"top_aud_k6_src_sel",
-"top_aud_k1_src_div",
-"top_aud_k2_src_div",
-"top_aud_k3_src_div",
-"top_aud_k4_src_div",
-"top_aud_k5_src_div",
-"top_aud_k6_src_div",
-"top_aud_i2s1_mclk",
-"top_aud_i2s2_mclk",
-"top_aud_i2s3_mclk",
-"top_aud_i2s4_mclk",
-"top_aud_i2s5_mclk",
-

[PATCH v2 08/12] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623

[sean.wang]

From: Ryder Lee 

Modify audio related nodes to reflect the actual usage in binding documents.

Signed-off-by: Ryder Lee 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt2701.dtsi | 188 -
 arch/arm/boot/dts/mt7623.dtsi | 190 --
 2 files changed, 182 insertions(+), 196 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index cf1c8eb..180377e 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -419,104 +419,96 @@
status = "disabled";
};
 
-   afe: audio-controller@1122 {
-   compatible = "mediatek,mt2701-audio";
-   reg = <0 0x1122 0 0x2000>,
- <0 0x112a 0 0x2>;
-   interrupts =  ,
- ;
-   interrupt-names = "afe", "asys";
-   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
-
-   clocks = < CLK_INFRA_AUDIO>,
-< CLK_TOP_AUD_MUX1_SEL>,
-< CLK_TOP_AUD_MUX2_SEL>,
-< CLK_TOP_AUD_MUX1_DIV>,
-< CLK_TOP_AUD_MUX2_DIV>,
-< CLK_TOP_AUD_48K_TIMING>,
-< CLK_TOP_AUD_44K_TIMING>,
-< CLK_TOP_AUDPLL_MUX_SEL>,
-< CLK_TOP_APLL_SEL>,
-< CLK_TOP_AUD1PLL_98M>,
-< CLK_TOP_AUD2PLL_90M>,
-< CLK_TOP_HADDS2PLL_98M>,
-< CLK_TOP_HADDS2PLL_294M>,
-< CLK_TOP_AUDPLL>,
-< CLK_TOP_AUDPLL_D4>,
-< CLK_TOP_AUDPLL_D8>,
-< CLK_TOP_AUDPLL_D16>,
-< CLK_TOP_AUDPLL_D24>,
-< CLK_TOP_AUDINTBUS_SEL>,
-<>,
-< CLK_TOP_SYSPLL1_D4>,
-< CLK_TOP_AUD_K1_SRC_SEL>,
-< CLK_TOP_AUD_K2_SRC_SEL>,
-< CLK_TOP_AUD_K3_SRC_SEL>,
-< CLK_TOP_AUD_K4_SRC_SEL>,
-< CLK_TOP_AUD_K5_SRC_SEL>,
-< CLK_TOP_AUD_K6_SRC_SEL>,
-< CLK_TOP_AUD_K1_SRC_DIV>,
-< CLK_TOP_AUD_K2_SRC_DIV>,
-< CLK_TOP_AUD_K3_SRC_DIV>,
-< CLK_TOP_AUD_K4_SRC_DIV>,
-< CLK_TOP_AUD_K5_SRC_DIV>,
-< CLK_TOP_AUD_K6_SRC_DIV>,
-< CLK_TOP_AUD_I2S1_MCLK>,
-< CLK_TOP_AUD_I2S2_MCLK>,
-< CLK_TOP_AUD_I2S3_MCLK>,
-< CLK_TOP_AUD_I2S4_MCLK>,
-< CLK_TOP_AUD_I2S5_MCLK>,
-< CLK_TOP_AUD_I2S6_MCLK>,
-< CLK_TOP_ASM_M_SEL>,
-< CLK_TOP_ASM_H_SEL>,
-< CLK_TOP_UNIVPLL2_D4>,
-< CLK_TOP_UNIVPLL2_D2>,
-< CLK_TOP_SYSPLL_D5>;
-
-   clock-names = "infra_sys_audio_clk",
-"top_audio_mux1_sel",
-"top_audio_mux2_sel",
-"top_audio_mux1_div",
-"top_audio_mux2_div",
-"top_audio_48k_timing",
-"top_audio_44k_timing",
-"top_audpll_mux_sel",
-"top_apll_sel",
-"top_aud1_pll_98M",
-"top_aud2_pll_90M",
-"top_hadds2_pll_98M",
-"top_hadds2_pll_294M",
-"top_audpll",
-"top_audpll_d4",
-"top_audpll_d8",
-"top_audpll_d16",
-"top_audpll_d24",
-"top_audintbus_sel",
-"clk_26m",
-"top_syspll1_d4",
-"top_aud_k1_src_sel",
-"top_aud_k2_src_sel",
-"top_aud_k3_src_sel",
-"top_aud_k4_src_sel",
-"top_aud_k5_src_sel",
-"top_aud_k6_src_sel",
-"top_aud_k1_src_div",
-"top_aud_k2_src_div",
-"top_aud_k3_src_div",
-"top_aud_k4_src_div",
-"top_aud_k5_src_div",
-"top_aud_k6_src_div",
-"top_aud_i2s1_mclk",
-"top_aud_i2s2_mclk",
-"top_aud_i2s3_mclk",
-"top_aud_i2s4_mclk",
-"top_aud_i2s5_mclk",
-"top_aud_i2s6_mclk",
-"top_asm_m_sel",
-