Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-07-18 Thread Manivannan Sadhasivam 
On Wed, Apr 18, 2018 at 07:16:01PM +0530, Manivannan Sadhasivam wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
> 
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
> 
> Signed-off-by: Manivannan Sadhasivam 

Hi Andy,

Any update on this patch? We have got 3 reviews so far...

Thanks,
Mani

> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>  
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
>   aliases {
>   serial0 = _uart1;
> @@ -90,6 +117,218 @@
>   status = "okay";
>   };
>  
> + pinctrl@101 {
> + gpio-line-names =
> + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
> pin 14 */
> + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
> */
> + "TP93", /* GPIO_9 */
> + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
> */
> + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> + "NC", /* GPIO_12 */
> + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> + "TP99", /* GPIO_16 */
> + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
> pin 34 */
> + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
> pin 32 */
> + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
> + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
> + "GPIO-D", /* GPIO_24, LSEC pin 26 */
> + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
> + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
> 32 */
> + "BLSP6_I2C_SDA", /* GPIO_27 */
> + "BLSP6_I2C_SCL", /* GPIO_28 */
> + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 
> */
> + "GPIO30", /* GPIO_30, S

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-07-18 Thread Manivannan Sadhasivam 
On Wed, Apr 18, 2018 at 07:16:01PM +0530, Manivannan Sadhasivam wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
> 
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
> 
> Signed-off-by: Manivannan Sadhasivam 

Hi Andy,

Any update on this patch? We have got 3 reviews so far...

Thanks,
Mani

> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>  
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
>   aliases {
>   serial0 = _uart1;
> @@ -90,6 +117,218 @@
>   status = "okay";
>   };
>  
> + pinctrl@101 {
> + gpio-line-names =
> + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
> pin 14 */
> + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
> */
> + "TP93", /* GPIO_9 */
> + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
> */
> + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> + "NC", /* GPIO_12 */
> + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> + "TP99", /* GPIO_16 */
> + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
> pin 34 */
> + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
> pin 32 */
> + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
> + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
> + "GPIO-D", /* GPIO_24, LSEC pin 26 */
> + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
> + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
> 32 */
> + "BLSP6_I2C_SDA", /* GPIO_27 */
> + "BLSP6_I2C_SCL", /* GPIO_28 */
> + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 
> */
> + "GPIO30", /* GPIO_30, S

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-07-09 Thread Amit Kucheria 
On Wed, Apr 18, 2018 at 7:16 PM, Manivannan Sadhasivam
 wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
>
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
>
> Signed-off-by: Manivannan Sadhasivam 

FWIW,

Reviewed-by: Amit Kucheria 

> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
> aliases {
> serial0 = _uart1;
> @@ -90,6 +117,218 @@
> status = "okay";
> };
>
> +   pinctrl@101 {
> +   gpio-line-names =
> +   "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, 
> LSEC pin 14 */
> +   "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> +   "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> +   "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> +   "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> +   "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> +   "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> +   "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> +   "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 
> 30 */
> +   "TP93", /* GPIO_9 */
> +   "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 
> 29 */
> +   "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> +   "NC", /* GPIO_12 */
> +   "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> +   "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> +   "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> +   "TP99", /* GPIO_16 */
> +   "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P 
> HSEC pin 34 */
> +   "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P 
> HSEC pin 32 */
> +   "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> +   "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> +   "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> +   "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 
> */
> +   "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 
> */
> +   "GPIO-D", /* GPIO_24, LSEC pin 26 */
> +   "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 
> */
> +   "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC 
> pin 32 */
> +   "BLSP6_I2C_SDA", /* GPIO_27 */
> +   "BLSP6_I2C_SCL", /* GPIO_28 */
> +   "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 
> 24 */
> +

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-07-09 Thread Amit Kucheria 
On Wed, Apr 18, 2018 at 7:16 PM, Manivannan Sadhasivam
 wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
>
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
>
> Signed-off-by: Manivannan Sadhasivam 

FWIW,

Reviewed-by: Amit Kucheria 

> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
> aliases {
> serial0 = _uart1;
> @@ -90,6 +117,218 @@
> status = "okay";
> };
>
> +   pinctrl@101 {
> +   gpio-line-names =
> +   "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, 
> LSEC pin 14 */
> +   "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> +   "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> +   "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> +   "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> +   "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> +   "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> +   "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> +   "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 
> 30 */
> +   "TP93", /* GPIO_9 */
> +   "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 
> 29 */
> +   "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> +   "NC", /* GPIO_12 */
> +   "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> +   "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> +   "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> +   "TP99", /* GPIO_16 */
> +   "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P 
> HSEC pin 34 */
> +   "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P 
> HSEC pin 32 */
> +   "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> +   "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> +   "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> +   "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 
> */
> +   "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 
> */
> +   "GPIO-D", /* GPIO_24, LSEC pin 26 */
> +   "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 
> */
> +   "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC 
> pin 32 */
> +   "BLSP6_I2C_SDA", /* GPIO_27 */
> +   "BLSP6_I2C_SCL", /* GPIO_28 */
> +   "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 
> 24 */
> +

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-05-16 Thread Linus Walleij 
On Wed, Apr 18, 2018 at 3:46 PM, Manivannan Sadhasivam
 wrote:

> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
>
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
>
> Signed-off-by: Manivannan Sadhasivam 

Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-05-16 Thread Linus Walleij 
On Wed, Apr 18, 2018 at 3:46 PM, Manivannan Sadhasivam
 wrote:

> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
>
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
>
> Signed-off-by: Manivannan Sadhasivam 

Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-05-09 Thread Todor Tomov 
Hi Mani,

On 18.04.2018 16:46, Manivannan Sadhasivam wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
> 
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
> 
> Signed-off-by: Manivannan Sadhasivam 

Thank you for adding the schematic names to the comments.
You can have my:
Reviewed-by: Todor Tomov 


> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>  
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
>   aliases {
>   serial0 = _uart1;
> @@ -90,6 +117,218 @@
>   status = "okay";
>   };
>  
> + pinctrl@101 {
> + gpio-line-names =
> + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
> pin 14 */
> + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
> */
> + "TP93", /* GPIO_9 */
> + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
> */
> + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> + "NC", /* GPIO_12 */
> + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> + "TP99", /* GPIO_16 */
> + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
> pin 34 */
> + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
> pin 32 */
> + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
> + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
> + "GPIO-D", /* GPIO_24, LSEC pin 26 */
> + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
> + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
> 32 */
> + "BLSP6_I2C_SDA", /* GPIO_27 */
> + "BLSP6_I2C_SCL", /* GPIO_28 */
> + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin

Re: [PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-05-09 Thread Todor Tomov 
Hi Mani,

On 18.04.2018 16:46, Manivannan Sadhasivam wrote:
> Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
> There are 4 gpio-controllers present on this board, including the
> APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).
> 
> Lines names are derived from 96Boards CE Specification 1.0, Appendix
> "Expansion Connector Signal Description". Line names for PMI8994 MPP
> pins are not added due to the absence of the gpio-controller support.
> 
> Signed-off-by: Manivannan Sadhasivam 

Thank you for adding the schematic names to the comments.
You can have my:
Reviewed-by: Todor Tomov 


> ---
>  arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 
> +++
>  1 file changed, 239 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
> b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> index 1c8f1b86472d..473530527e27 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
> @@ -19,6 +19,33 @@
>  #include 
>  #include 
>  
> +/*
> + * GPIO name legend: proper name = the GPIO line is used as GPIO
> + * NC  = not connected (pin out but not routed from the chip to
> + *   anything the board)
> + * "[PER]" = pin is muxed for [peripheral] (not GPIO)
> + * LSEC= Low Speed External Connector
> + * P HSEC  = Primary High Speed External Connector
> + * S HSEC  = Secondary High Speed External Connector
> + * J14 = Camera Connector
> + * TP  = Test Points
> + *
> + * Line names are taken from the schematic "DragonBoard 820c",
> + * drawing no: LM25-P2751-1
> + *
> + * For the lines routed to the external connectors the
> + * lines are named after the 96Boards CE Specification 1.0,
> + * Appendix "Expansion Connector Signal Description".
> + *
> + * When the 96Board naming of a line and the schematic name of
> + * the same line are in conflict, the 96Board specification
> + * takes precedence, which means that the external UART on the
> + * LSEC is named UART0 while the schematic and SoC names this
> + * UART3. This is only for the informational lines i.e. "[FOO]",
> + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
> + * ones actually used for GPIO.
> + */
> +
>  / {
>   aliases {
>   serial0 = _uart1;
> @@ -90,6 +117,218 @@
>   status = "okay";
>   };
>  
> + pinctrl@101 {
> + gpio-line-names =
> + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
> pin 14 */
> + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
> pin 10 */
> + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
> pin 12 */
> + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
> pin 8 */
> + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
> pin 11 */
> + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
> pin 13 */
> + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
> pin 21 */
> + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
> pin 19 */
> + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
> */
> + "TP93", /* GPIO_9 */
> + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
> */
> + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
> + "NC", /* GPIO_12 */
> + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
> pin 15 */
> + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
> + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
> pin 17 */
> + "TP99", /* GPIO_16 */
> + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
> pin 34 */
> + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
> pin 32 */
> + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
> + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
> + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
> + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
> + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
> + "GPIO-D", /* GPIO_24, LSEC pin 26 */
> + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
> + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
> 32 */
> + "BLSP6_I2C_SDA", /* GPIO_27 */
> + "BLSP6_I2C_SCL", /* GPIO_28 */
> + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 
> */
> + "GPIO30", /*

[PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-04-18 Thread Manivannan Sadhasivam 
Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
There are 4 gpio-controllers present on this board, including the
APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).

Lines names are derived from 96Boards CE Specification 1.0, Appendix
"Expansion Connector Signal Description". Line names for PMI8994 MPP
pins are not added due to the absence of the gpio-controller support.

Signed-off-by: Manivannan Sadhasivam 
---
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 +++
 1 file changed, 239 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 1c8f1b86472d..473530527e27 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -19,6 +19,33 @@
 #include 
 #include 
 
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC  = not connected (pin out but not routed from the chip to
+ *   anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC= Low Speed External Connector
+ * P HSEC  = Primary High Speed External Connector
+ * S HSEC  = Secondary High Speed External Connector
+ * J14 = Camera Connector
+ * TP  = Test Points
+ *
+ * Line names are taken from the schematic "DragonBoard 820c",
+ * drawing no: LM25-P2751-1
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
 / {
aliases {
serial0 = _uart1;
@@ -90,6 +117,218 @@
status = "okay";
};
 
+   pinctrl@101 {
+   gpio-line-names =
+   "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
pin 14 */
+   "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
pin 10 */
+   "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
pin 12 */
+   "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
pin 8 */
+   "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
pin 11 */
+   "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
pin 13 */
+   "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
pin 21 */
+   "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
pin 19 */
+   "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
*/
+   "TP93", /* GPIO_9 */
+   "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
*/
+   "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
+   "NC", /* GPIO_12 */
+   "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
pin 15 */
+   "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
+   "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
pin 17 */
+   "TP99", /* GPIO_16 */
+   "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
pin 34 */
+   "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
pin 32 */
+   "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
+   "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
+   "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
+   "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
+   "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
+   "GPIO-D", /* GPIO_24, LSEC pin 26 */
+   "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
+   "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
32 */
+   "BLSP6_I2C_SDA", /* GPIO_27 */
+   "BLSP6_I2C_SCL", /* GPIO_28 */
+   "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 
*/
+   "GPIO30", /* GPIO_30, S HSEC pin 4 */
+   "HDMI_CEC", /* GPIO_31 */
+   "HDMI_DDC_CLOCK", /* GPIO_32 */
+   "HDMI_DDC_DATA", /* GPIO_33 */
+   "HDMI_HOT_PLUG_DETECT", /*

[PATCH v2 1/1] dts: qcom: db820c: Add gpio-line-names property

2018-04-18 Thread Manivannan Sadhasivam 
Add gpio-line-names property for Dragonboard820c based on APQ8096 SoC.
There are 4 gpio-controllers present on this board, including the
APQ8096 SoC, PM8994 (GPIO and MPP) and PMI8994 (GPIO).

Lines names are derived from 96Boards CE Specification 1.0, Appendix
"Expansion Connector Signal Description". Line names for PMI8994 MPP
pins are not added due to the absence of the gpio-controller support.

Signed-off-by: Manivannan Sadhasivam 
---
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 +++
 1 file changed, 239 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi 
b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 1c8f1b86472d..473530527e27 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -19,6 +19,33 @@
 #include 
 #include 
 
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC  = not connected (pin out but not routed from the chip to
+ *   anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC= Low Speed External Connector
+ * P HSEC  = Primary High Speed External Connector
+ * S HSEC  = Secondary High Speed External Connector
+ * J14 = Camera Connector
+ * TP  = Test Points
+ *
+ * Line names are taken from the schematic "DragonBoard 820c",
+ * drawing no: LM25-P2751-1
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
 / {
aliases {
serial0 = _uart1;
@@ -90,6 +117,218 @@
status = "okay";
};
 
+   pinctrl@101 {
+   gpio-line-names =
+   "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC 
pin 14 */
+   "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC 
pin 10 */
+   "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC 
pin 12 */
+   "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC 
pin 8 */
+   "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC 
pin 11 */
+   "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC 
pin 13 */
+   "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC 
pin 21 */
+   "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC 
pin 19 */
+   "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 
*/
+   "TP93", /* GPIO_9 */
+   "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 
*/
+   "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
+   "NC", /* GPIO_12 */
+   "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC 
pin 15 */
+   "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
+   "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC 
pin 17 */
+   "TP99", /* GPIO_16 */
+   "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC 
pin 34 */
+   "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC 
pin 32 */
+   "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
+   "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
+   "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
+   "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
+   "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
+   "GPIO-D", /* GPIO_24, LSEC pin 26 */
+   "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
+   "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 
32 */
+   "BLSP6_I2C_SDA", /* GPIO_27 */
+   "BLSP6_I2C_SCL", /* GPIO_28 */
+   "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 
*/
+   "GPIO30", /* GPIO_30, S HSEC pin 4 */
+   "HDMI_CEC", /* GPIO_31 */
+   "HDMI_DDC_CLOCK", /* GPIO_32 */
+   "HDMI_DDC_DATA", /* GPIO_33 */
+   "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
+