Add support for the base Device Tree for Imagination Technologies'
Pistachio SoC.
This commit supports the following peripherals:
* Clocks
* Pinctrl and GPIO
* UART
* SPI
* I2C
* PWM
* ADC
* Watchdog
* Ethernet
* MMC
* DMA engine
* Crypto
* I2S
* SPDIF
* Internal DAC
* Timer
* USB
* IR
* Interrupt Controller
Signed-off-by: Rahul Bedarkar
---
Changes in v2:
- No change
---
MAINTAINERS | 2 +-
arch/mips/boot/dts/img/pistachio.dtsi | 924 ++
2 files changed, 925 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/img/pistachio.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 207eaef..98bcf06 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9509,7 +9509,7 @@ L: linux-m...@linux-mips.org
S: Maintained
F: arch/mips/pistachio/
F: arch/mips/include/asm/mach-pistachio/
-F: arch/mips/boot/dts/pistachio/
+F: arch/mips/boot/dts/img/pistachio*
F: arch/mips/configs/pistachio*_defconfig
PKTCDVD DRIVER
diff --git a/arch/mips/boot/dts/img/pistachio.dtsi
b/arch/mips/boot/dts/img/pistachio.dtsi
new file mode 100644
index 000..57809f6
--- /dev/null
+++ b/arch/mips/boot/dts/img/pistachio.dtsi
@@ -0,0 +1,924 @@
+/*
+ * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "img,pistachio";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "mti,interaptiv";
+ reg = <0>;
+ clocks = <&clk_core CLK_MIPS_PLL>;
+ clock-names = "cpu";
+ clock-latency = <1000>;
+ operating-points = <
+ /* kHzuV(dummy) */
+ 546000 115
+ 52 110
+ 494000 100
+ 468000 95
+ 442000 90
+ 416000 80
+ >;
+ };
+ };
+
+ i2c0: i2c@1810 {
+ compatible = "img,scb-i2c";
+ reg = <0x1810 0x200>;
+ interrupts = ;
+ clocks = <&clk_periph PERIPH_CLK_I2C0>,
+<&cr_periph SYS_CLK_I2C0>;
+ clock-names = "scb", "sys";
+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
+ <&clk_periph PERIPH_CLK_I2C0_DIV>;
+ assigned-clock-rates = <1>, <3334>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@18100200 {
+ compatible = "img,scb-i2c";
+ reg = <0x18100200 0x200>;
+ interrupts = ;
+ clocks = <&clk_periph PERIPH_CLK_I2C1>,
+<&cr_periph SYS_CLK_I2C1>;
+ clock-names = "scb", "sys";
+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
+ <&clk_periph PERIPH_CLK_I2C1_DIV>;
+ assigned-clock-rates = <1>, <3334>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@18100400 {
+ compatible = "img,scb-i2c";
+ reg = <0x18100400 0x200>;
+ interrupts = ;
+ clocks = <&clk_periph PERIPH_CLK_I2C2>,
+<&cr_periph SYS_CLK_I2C2>;
+ clock-names = "scb", "sys";
+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
+ <&clk_periph PERIPH_CLK_I2C2_DIV>;
+ assigned-clock-rates = <1>, <3334>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@18100600 {
+ compatible = "img,scb-i2c";
+ reg = <0x18100600 0x200>;
+ interrupts = ;
+ clocks = <&clk_periph PERIPH_CLK_I2C3>,
+<&cr_periph SYS_CLK_I2C3>;
+