Re: [PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

On Thu, Apr 12, 2018 at 10:36:21AM +0100, Matt Redfearn wrote: > Processors implementing the MIPS MT ASE may have performance counters > implemented per core or per TC. Processors implemented by MIPS > Technologies signify presence per TC through a bit in the implementation > specific Config7

Re: [PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

On Thu, Apr 12, 2018 at 10:36:21AM +0100, Matt Redfearn wrote: > Processors implementing the MIPS MT ASE may have performance counters > implemented per core or per TC. Processors implemented by MIPS > Technologies signify presence per TC through a bit in the implementation > specific Config7

[PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

Processors implementing the MIPS MT ASE may have performance counters implemented per core or per TC. Processors implemented by MIPS Technologies signify presence per TC through a bit in the implementation specific Config7 register. Currently the code which probes for their presence blindly reads

[PATCH v2 1/6] MIPS: perf: More robustly probe for the presence of per-tc counters

Processors implementing the MIPS MT ASE may have performance counters implemented per core or per TC. Processors implemented by MIPS Technologies signify presence per TC through a bit in the implementation specific Config7 register. Currently the code which probes for their presence blindly reads