subject:"\[PATCH v2 2\/2\] soc\: mediatek\: pm\-domains\: Add support for mt8167"

Re: [PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8167

2020-10-30 Thread Enric Balletbo i Serra

Hi Fabien,

Thank you for the patch and base it on the new SCPSYS PM domains driver

On 27/10/20 14:11, Fabien Parent wrote:
> Add the needed board data to support mt8167 SoC.
> 
> Signed-off-by: Fabien Parent 
> ---
> 
> This patch depends on the SCPSYS PM domains driver [0].
> 
> v2:
>   * Implement on top of new SCPSYS PM domains driver [0]
> 
> [0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=370737
>  drivers/soc/mediatek/mt8167-pm-domains.h | 86 
>  drivers/soc/mediatek/mtk-pm-domains.c|  5 ++
>  drivers/soc/mediatek/mtk-pm-domains.h|  1 +
>  include/linux/soc/mediatek/infracfg.h|  8 +++
>  4 files changed, 100 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8167-pm-domains.h
> 
> diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h 
> b/drivers/soc/mediatek/mt8167-pm-domains.h
> new file mode 100644
> index ..ff18139d0d6c
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8167-pm-domains.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
> +#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
> +
> +#include "mtk-pm-domains.h"
> +#include 
> +
> +#define MT8167_PWR_STATUS_MFG_2D BIT(24)
> +#define MT8167_PWR_STATUS_MFG_ASYNC  BIT(25)
> +
> +/*
> + * MT8167 power domain support
> + */
> +
> +static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
> + [MT8167_POWER_DOMAIN_DISP] = {
> + .sta_mask = PWR_STATUS_DISP,
> + .ctl_offs = SPM_DIS_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_infracfg = {
> + BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
> +MT8167_TOP_AXI_PROT_EN_MCU_MM),
> + },
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8167_POWER_DOMAIN_VDEC] = {
> + .sta_mask = PWR_STATUS_VDEC,
> + .ctl_offs = SPM_VDE_PWR_CON,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8167_POWER_DOMAIN_ISP] = {
> + .sta_mask = PWR_STATUS_ISP,
> + .ctl_offs = SPM_ISP_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
> + .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
> + .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .bp_infracfg = {
> + BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
> +MT8167_TOP_AXI_PROT_EN_MFG_EMI),
> + },
> + },
> + [MT8167_POWER_DOMAIN_MFG_2D] = {
> + .sta_mask = MT8167_PWR_STATUS_MFG_2D,
> + .ctl_offs = SPM_MFG_2D_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(15, 12),
> + },
> + [MT8167_POWER_DOMAIN_MFG] = {
> + .sta_mask = PWR_STATUS_MFG,
> + .ctl_offs = SPM_MFG_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(15, 12),
> + },
> + [MT8167_POWER_DOMAIN_CONN] = {
> + .sta_mask = PWR_STATUS_CONN,
> + .ctl_offs = SPM_CONN_PWR_CON,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + .bp_infracfg = {
> + BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
> +MT8167_TOP_AXI_PROT_EN_CONN_MCU |
> +MT8167_TOP_AXI_PROT_EN_MCU_CONN),
> + },
> + },
> +};
> +
> +static const struct scpsys_soc_data mt8167_scpsys_data = {
> + .domains = scpsys_domain_data_mt8167,

Just to let you know, this is now domains_data.

> + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
> + .pwr_sta_offs = SPM_PWR_STATUS,
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
> +
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c 
> b/drivers/soc/mediatek/mtk-pm-domains.c
> index 293efa27b6ce..34c704865f01 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  
> +#include "mt8167-pm-domains.h"
>  #include "mt8173-pm-domains.h"
>  #include "mt8183-pm-domains.h"
>  #include "mt8192-pm-domains.h"
> @@ -515,6 +516,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
>  }
>  
>  static const struct of_device_id scpsys_of_match[] = {
> + {
> +

[PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8167

2020-10-27 Thread Fabien Parent

Add the needed board data to support mt8167 SoC.

Signed-off-by: Fabien Parent 
---

This patch depends on the SCPSYS PM domains driver [0].

v2:
* Implement on top of new SCPSYS PM domains driver [0]

[0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=370737
 drivers/soc/mediatek/mt8167-pm-domains.h | 86 
 drivers/soc/mediatek/mtk-pm-domains.c|  5 ++
 drivers/soc/mediatek/mtk-pm-domains.h|  1 +
 include/linux/soc/mediatek/infracfg.h|  8 +++
 4 files changed, 100 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8167-pm-domains.h

diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h 
b/drivers/soc/mediatek/mt8167-pm-domains.h
new file mode 100644
index ..ff18139d0d6c
--- /dev/null
+++ b/drivers/soc/mediatek/mt8167-pm-domains.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include 
+
+#define MT8167_PWR_STATUS_MFG_2D   BIT(24)
+#define MT8167_PWR_STATUS_MFG_ASYNCBIT(25)
+
+/*
+ * MT8167 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
+   [MT8167_POWER_DOMAIN_DISP] = {
+   .sta_mask = PWR_STATUS_DISP,
+   .ctl_offs = SPM_DIS_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .bp_infracfg = {
+   BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
+  MT8167_TOP_AXI_PROT_EN_MCU_MM),
+   },
+   .caps = MTK_SCPD_ACTIVE_WAKEUP,
+   },
+   [MT8167_POWER_DOMAIN_VDEC] = {
+   .sta_mask = PWR_STATUS_VDEC,
+   .ctl_offs = SPM_VDE_PWR_CON,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .caps = MTK_SCPD_ACTIVE_WAKEUP,
+   },
+   [MT8167_POWER_DOMAIN_ISP] = {
+   .sta_mask = PWR_STATUS_ISP,
+   .ctl_offs = SPM_ISP_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(13, 12),
+   .caps = MTK_SCPD_ACTIVE_WAKEUP,
+   },
+   [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
+   .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
+   .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+   .sram_pdn_bits = 0,
+   .sram_pdn_ack_bits = 0,
+   .bp_infracfg = {
+   BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
+  MT8167_TOP_AXI_PROT_EN_MFG_EMI),
+   },
+   },
+   [MT8167_POWER_DOMAIN_MFG_2D] = {
+   .sta_mask = MT8167_PWR_STATUS_MFG_2D,
+   .ctl_offs = SPM_MFG_2D_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(15, 12),
+   },
+   [MT8167_POWER_DOMAIN_MFG] = {
+   .sta_mask = PWR_STATUS_MFG,
+   .ctl_offs = SPM_MFG_PWR_CON,
+   .sram_pdn_bits = GENMASK(11, 8),
+   .sram_pdn_ack_bits = GENMASK(15, 12),
+   },
+   [MT8167_POWER_DOMAIN_CONN] = {
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = SPM_CONN_PWR_CON,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = 0,
+   .caps = MTK_SCPD_ACTIVE_WAKEUP,
+   .bp_infracfg = {
+   BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
+  MT8167_TOP_AXI_PROT_EN_CONN_MCU |
+  MT8167_TOP_AXI_PROT_EN_MCU_CONN),
+   },
+   },
+};
+
+static const struct scpsys_soc_data mt8167_scpsys_data = {
+   .domains = scpsys_domain_data_mt8167,
+   .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
+   .pwr_sta_offs = SPM_PWR_STATUS,
+   .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+};
+
+#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
+
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c 
b/drivers/soc/mediatek/mtk-pm-domains.c
index 293efa27b6ce..34c704865f01 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 
+#include "mt8167-pm-domains.h"
 #include "mt8173-pm-domains.h"
 #include "mt8183-pm-domains.h"
 #include "mt8192-pm-domains.h"
@@ -515,6 +516,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
 }
 
 static const struct of_device_id scpsys_of_match[] = {
+   {
+   .compatible = "mediatek,mt8167-power-controller",
+   .data = _scpsys_data,
+   },
{
.compatible = "mediatek,mt8173-power-controller",
.data = _scpsys_data,
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h

Re: [PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8167

[PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8167

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