[PATCH v2 2/4] phy: phy-mt65xx-usb3: add SATA PHY support

2017-08-08 Thread Chunfeng Yun 
From: Ryder Lee 

This patch adds SATA setting part.

Signed-off-by: Ryder Lee 
Signed-off-by: Chunfeng Yun 
---
 drivers/phy/phy-mt65xx-usb3.c | 133 --
 1 file changed, 129 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index a9a85fa..5e9a415 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -29,7 +29,7 @@
 #define SSUSB_SIFSLV_V1_U2FREQ 0x100   /* shared by u2 phys */
 /* u2 phy bank */
 #define SSUSB_SIFSLV_V1_U2PHY_COM  0x000
-/* u3/pcie phy banks */
+/* u3/pcie/sata phy banks */
 #define SSUSB_SIFSLV_V1_U3PHYD 0x000
 #define SSUSB_SIFSLV_V1_U3PHYA 0x200
 
@@ -199,6 +199,65 @@
 #define U3P_SR_COEF_DIVISOR1000
 #define U3P_FM_DET_CYCLE_CNT   1024
 
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSKGENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSKGENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION20x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSKGENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION90x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK  GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x)   ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK  GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x)   ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK  GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x)   ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK  GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x)   (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL10x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK   GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL40x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x)  ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x)  ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL60x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x)  ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x)  (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL10x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSKGENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL40xd8
+#define RG_CDR_BIRLTD0_GEN1_MSKGENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL50xdc
+#define RG_CDR_BIRLTD0_GEN3_MSKGENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
 enum mt_phy_version {
MT_PHY_V1 = 1,
MT_PHY_V2,
@@ -630,6 +689,64 @@ static void pcie_phy_instance_power_off(struct 
mt65xx_u3phy *u3phy,
writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 }
 
+static void sata_phy_instance_init(struct mt65xx_u3phy *u3phy,
+  struct mt65xx_phy_instance *instance)
+{
+   struct u3phy_banks *u3_banks = >u3_banks;
+   void __iomem *phyd = u3_banks->phyd;
+   u32 tmp;
+
+   /* charge current adjustment */
+   tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
+   tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
+   tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
+   writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
+
+   tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
+   tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
+   tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
+   writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
+
+   tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
+   tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
+   tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
+   writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
+
+   tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
+   tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
+   tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
+   writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
+
+   tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
+   tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
+   tmp |=

[PATCH v2 2/4] phy: phy-mt65xx-usb3: add SATA PHY support

2017-08-08 Thread Chunfeng Yun 
From: Ryder Lee 

This patch adds SATA setting part.

Signed-off-by: Ryder Lee 
Signed-off-by: Chunfeng Yun 
---
 drivers/phy/phy-mt65xx-usb3.c | 133 --
 1 file changed, 129 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index a9a85fa..5e9a415 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -29,7 +29,7 @@
 #define SSUSB_SIFSLV_V1_U2FREQ 0x100   /* shared by u2 phys */
 /* u2 phy bank */
 #define SSUSB_SIFSLV_V1_U2PHY_COM  0x000
-/* u3/pcie phy banks */
+/* u3/pcie/sata phy banks */
 #define SSUSB_SIFSLV_V1_U3PHYD 0x000
 #define SSUSB_SIFSLV_V1_U3PHYA 0x200
 
@@ -199,6 +199,65 @@
 #define U3P_SR_COEF_DIVISOR1000
 #define U3P_FM_DET_CYCLE_CNT   1024
 
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSKGENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSKGENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION20x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSKGENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION90x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK  GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x)   ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK  GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x)   ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK  GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x)   ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK  GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x)   (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL10x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK   GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL40x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x)  ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x)  ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL60x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x)  ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x)  (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL10x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSKGENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL40xd8
+#define RG_CDR_BIRLTD0_GEN1_MSKGENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL50xdc
+#define RG_CDR_BIRLTD0_GEN3_MSKGENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
 enum mt_phy_version {
MT_PHY_V1 = 1,
MT_PHY_V2,
@@ -630,6 +689,64 @@ static void pcie_phy_instance_power_off(struct 
mt65xx_u3phy *u3phy,
writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 }
 
+static void sata_phy_instance_init(struct mt65xx_u3phy *u3phy,
+  struct mt65xx_phy_instance *instance)
+{
+   struct u3phy_banks *u3_banks = >u3_banks;
+   void __iomem *phyd = u3_banks->phyd;
+   u32 tmp;
+
+   /* charge current adjustment */
+   tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
+   tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
+   tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
+   writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
+
+   tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
+   tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
+   tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
+   writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
+
+   tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
+   tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
+   tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
+   writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
+
+   tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
+   tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
+   tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
+   writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
+
+   tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
+   tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
+   tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
+   writel(tmp, phyd +