Re: [PATCH v2 4/4] clk: qcom: Add graphics clock controller driver for SDM845
Hi Amit,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on agross/for-next]
[also build test ERROR on v4.18-rc4 next-20180713]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Amit-Nischal/Add-QCOM-graphics-clock-controller-driver-for-SDM845/20180714-080708
base: https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
for-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
>> drivers/clk/qcom/gpucc-sdm845.c:136:2: error: implicit declaration of
>> function 'F'; did you mean 'FS'? [-Werror=implicit-function-declaration]
F(1920, P_BI_TCXO, 1, 0, 0),
^
FS
drivers/clk/qcom/gpucc-sdm845.c:136:2: error: initializer element is not
constant
drivers/clk/qcom/gpucc-sdm845.c:136:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].freq')
drivers/clk/qcom/gpucc-sdm845.c:137:2: error: initializer element is not
constant
F(2, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
^
drivers/clk/qcom/gpucc-sdm845.c:137:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].src')
drivers/clk/qcom/gpucc-sdm845.c:138:2: error: initializer element is not
constant
F(5, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
^
drivers/clk/qcom/gpucc-sdm845.c:138:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].pre_div')
drivers/clk/qcom/gpucc-sdm845.c:139:2: warning: braces around scalar
initializer
{ }
^
drivers/clk/qcom/gpucc-sdm845.c:139:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].m')
cc1: some warnings being treated as errors
vim +136 drivers/clk/qcom/gpucc-sdm845.c
134
135 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
> 136 F(1920, P_BI_TCXO, 1, 0, 0),
137 F(2, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
138 F(5, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
139 { }
140 };
141
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH v2 4/4] clk: qcom: Add graphics clock controller driver for SDM845
Hi Amit,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on agross/for-next]
[also build test ERROR on v4.18-rc4 next-20180713]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Amit-Nischal/Add-QCOM-graphics-clock-controller-driver-for-SDM845/20180714-080708
base: https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
for-next
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=xtensa
All error/warnings (new ones prefixed by >>):
>> drivers/clk/qcom/gpucc-sdm845.c:136:2: error: implicit declaration of
>> function 'F' [-Werror=implicit-function-declaration]
F(1920, P_BI_TCXO, 1, 0, 0),
^
>> drivers/clk/qcom/gpucc-sdm845.c:136:2: error: initializer element is not
>> constant
drivers/clk/qcom/gpucc-sdm845.c:136:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].freq')
drivers/clk/qcom/gpucc-sdm845.c:137:2: error: initializer element is not
constant
F(2, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
^
drivers/clk/qcom/gpucc-sdm845.c:137:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].src')
drivers/clk/qcom/gpucc-sdm845.c:138:2: error: initializer element is not
constant
F(5, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
^
drivers/clk/qcom/gpucc-sdm845.c:138:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].pre_div')
>> drivers/clk/qcom/gpucc-sdm845.c:139:2: warning: braces around scalar
>> initializer
{ }
^
drivers/clk/qcom/gpucc-sdm845.c:139:2: note: (near initialization for
'ftbl_gpu_cc_gmu_clk_src[0].m')
cc1: some warnings being treated as errors
vim +/F +136 drivers/clk/qcom/gpucc-sdm845.c
134
135 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
> 136 F(1920, P_BI_TCXO, 1, 0, 0),
137 F(2, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
138 F(5, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
> 139 { }
140 };
141
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
[PATCH v2 4/4] clk: qcom: Add graphics clock controller driver for SDM845
Add support for the graphics clock controller found on SDM845
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal
---
drivers/clk/qcom/Kconfig| 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sdm845.c | 438
3 files changed, 448 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-sdm845.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9c3480d..193c2f5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -235,6 +235,15 @@ config SDM_GCC_845
Say Y if you want to use peripheral devices such as UART, SPI,
i2C, USB, UFS, SDDC, PCIe, etc.
+config SDM_GPUCC_845
+ tristate "SDM845 Graphics Clock Controller"
+ depends on COMMON_CLK_QCOM
+ select SDM_GCC_845
+ help
+ Support for the graphics clock controller on SDM845 devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config SDM_VIDEOCC_845
tristate "SDM845 Video Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 32d17c2..8aa2bc9 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
+obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
new file mode 100644
index 000..7a11b70
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "gdsc.h"
+
+#define CX_GMU_CBCR_SLEEP_MASK 0xf
+#define CX_GMU_CBCR_SLEEP_SHIFT4
+#define CX_GMU_CBCR_WAKE_MASK 0xf
+#define CX_GMU_CBCR_WAKE_SHIFT 8
+#define CLK_DIS_WAIT_SHIFT 12
+#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
+
+enum {
+ P_BI_TCXO,
+ P_CORE_BI_PLL_TEST_SE,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL0_OUT_MAIN_DIV,
+ P_GPU_CC_PLL0_OUT_EVEN,
+ P_GPU_CC_PLL0_OUT_MAIN,
+ P_GPU_CC_PLL0_OUT_ODD,
+ P_GPU_CC_PLL1_OUT_EVEN,
+ P_GPU_CC_PLL1_OUT_MAIN,
+ P_GPU_CC_PLL1_OUT_ODD,
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL0_OUT_MAIN, 1 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gpu_cc_parent_names_0[] = {
+ "bi_tcxo",
+ "gpu_cc_pll0",
+ "gpu_cc_pll1",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src",
+ "core_bi_pll_test_se",
+};
+
+static const struct parent_map gpu_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL0_OUT_EVEN, 1 },
+ { P_GPU_CC_PLL0_OUT_ODD, 2 },
+ { P_GPU_CC_PLL1_OUT_EVEN, 3 },
+ { P_GPU_CC_PLL1_OUT_ODD, 4 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gpu_cc_parent_names_1[] = {
+ "bi_tcxo",
+ "gpu_cc_pll0_out_even",
+ "gpu_cc_pll0_out_odd",
+ "gpu_cc_pll1_out_even",
+ "gpu_cc_pll1_out_odd",
+ "gcc_gpu_gpll0_clk_src",
+ "core_bi_pll_test_se",
+};
+
+static const struct alpha_pll_config gpu_cc_pll0_config = {
+ .l = 0x1d,
+ .alpha = 0x2aaa,
+};
+
+static const struct alpha_pll_config gpu_cc_pll1_config = {
+ .l = 0x1a,
+ .alpha = 0xaab,
+};
+
+static struct clk_alpha_pll gpu_cc_pll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_pll0",
+ .parent_names = (const char *[]){ "bi_tcxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_fabia_even[] = {
+ { 0x0, 1 },
+};
+
+static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_fabia_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_T
