Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-02-11 Thread H. Peter Anvin 
On 01/27/2015 08:53 AM, Ross Zwisler wrote:
> Add support for the new pcommit (persistent commit) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.
> 
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
> 
> The pcommit instruction ensures that data that has been flushed from the
> processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
> memory and is durable on the DIMM.  The primary use case for this is 
> persistent
> memory.
> 
> This function shows how to properly use clwb/clflushopt/clflush and
> pcommit with appropriate fencing:
> 
> void flush_and_commit_buffer(void *vaddr, unsigned int size)
> {
>   void *vend = vaddr + size - 1;
> 
>   for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
>   clwb(vaddr);
> 
>   /* Flush any possible final partial cacheline */
>   clwb(vend);
> 
>   /*
>* sfence to order clwb/clflushopt/clflush cache flushes
>* mfence via mb() also works
>*/
>   wmb();
> 
>   /* pcommit and the required sfence for ordering */
>   pcommit_sfence();
> }
> 
> After this function completes the data pointed to by vaddr is has been
> accepted to memory and will be durable if the vaddr points to
> persistent memory.
> 
> Pcommit must always be ordered by an mfence or sfence, so to help
> simplify things we include both the pcommit and the required sfence in
> the alternatives generated by pcommit_sfence().  The other option is to
> keep them separated, but on platforms that don't support pcommit this
> would then turn into:
> 
> void flush_and_commit_buffer(void *vaddr, unsigned int size)
> {
> void *vend = vaddr + size - 1;
> 
> for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
> clwb(vaddr);
> 
> /* Flush any possible final partial cacheline */
> clwb(vend);
> 
> /*
>  * sfence to order clwb/clflushopt/clflush cache flushes
>  * mfence via mb() also works
>  */
> wmb();
> 
> nop(); /* from pcommit(), via alternatives */
> 
> /*
>  * sfence to order pcommit
>  * mfence via mb() also works
>  */
> wmb();
> }
> 
> This is still correct, but now you've got two fences separated by only a
> nop.  With the commit and the fence together in pcommit_sfence() you
> avoid the final unneeded fence.

Acked-by: H. Peter Anvin 


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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-02-11 Thread H. Peter Anvin 
On 01/27/2015 08:53 AM, Ross Zwisler wrote:
 Add support for the new pcommit (persistent commit) instruction.  This
 instruction was announced in the document Intel Architecture
 Instruction Set Extensions Programming Reference with reference number
 319433-022.
 
 https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
 
 The pcommit instruction ensures that data that has been flushed from the
 processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
 memory and is durable on the DIMM.  The primary use case for this is 
 persistent
 memory.
 
 This function shows how to properly use clwb/clflushopt/clflush and
 pcommit with appropriate fencing:
 
 void flush_and_commit_buffer(void *vaddr, unsigned int size)
 {
   void *vend = vaddr + size - 1;
 
   for (; vaddr  vend; vaddr += boot_cpu_data.x86_clflush_size)
   clwb(vaddr);
 
   /* Flush any possible final partial cacheline */
   clwb(vend);
 
   /*
* sfence to order clwb/clflushopt/clflush cache flushes
* mfence via mb() also works
*/
   wmb();
 
   /* pcommit and the required sfence for ordering */
   pcommit_sfence();
 }
 
 After this function completes the data pointed to by vaddr is has been
 accepted to memory and will be durable if the vaddr points to
 persistent memory.
 
 Pcommit must always be ordered by an mfence or sfence, so to help
 simplify things we include both the pcommit and the required sfence in
 the alternatives generated by pcommit_sfence().  The other option is to
 keep them separated, but on platforms that don't support pcommit this
 would then turn into:
 
 void flush_and_commit_buffer(void *vaddr, unsigned int size)
 {
 void *vend = vaddr + size - 1;
 
 for (; vaddr  vend; vaddr += boot_cpu_data.x86_clflush_size)
 clwb(vaddr);
 
 /* Flush any possible final partial cacheline */
 clwb(vend);
 
 /*
  * sfence to order clwb/clflushopt/clflush cache flushes
  * mfence via mb() also works
  */
 wmb();
 
 nop(); /* from pcommit(), via alternatives */
 
 /*
  * sfence to order pcommit
  * mfence via mb() also works
  */
 wmb();
 }
 
 This is still correct, but now you've got two fences separated by only a
 nop.  With the commit and the fence together in pcommit_sfence() you
 avoid the final unneeded fence.

Acked-by: H. Peter Anvin h...@linux.intel.com


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RE: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Elliott, Robert (Server Storage) 


> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
> ow...@vger.kernel.org] On Behalf Of Ross Zwisler
> Sent: Tuesday, 27 January, 2015 10:54 AM
> To: linux-kernel@vger.kernel.org
> Cc: Ross Zwisler; H Peter Anvin; Ingo Molnar; Thomas Gleixner; Borislav
> Petkov
> Subject: [PATCH v3 1/2] x86: Add support for the pcommit instruction
> 
> Add support for the new pcommit (persistent commit) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.
> 
> https://software.intel.com/sites/default/files/managed/0d/53/319433-
> 022.pdf
> 
...
> ---
>  arch/x86/include/asm/cpufeature.h| 1 +
>  arch/x86/include/asm/special_insns.h | 8 
>  2 files changed, 9 insertions(+)

Should this patch series also add defines for the virtual 
machine control data structure changes?

1. Add the new VM-Execution Controls bit 21 as
SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
to arch/x86/include/asm/vmx.h.

2. Add the new exit reason of 64 (0x41) as
EXIT_REASON_PCOMMIT  64
to arch/x86/include/uapi/asm/vmx.h and (with a
VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.

3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.


---
Rob ElliottHP Server Storage


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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Borislav Petkov 
On Tue, Jan 27, 2015 at 09:53:50AM -0700, Ross Zwisler wrote:
> Add support for the new pcommit (persistent commit) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.
> 
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
> 
> The pcommit instruction ensures that data that has been flushed from the
> processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
> memory and is durable on the DIMM.  The primary use case for this is 
> persistent
> memory.
> 
> This function shows how to properly use clwb/clflushopt/clflush and
> pcommit with appropriate fencing:

...

> This is still correct, but now you've got two fences separated by only a
> nop.  With the commit and the fence together in pcommit_sfence() you
> avoid the final unneeded fence.
> 
> Signed-off-by: Ross Zwisler 
> Cc: H Peter Anvin 
> Cc: Ingo Molnar 
> Cc: Thomas Gleixner 
> Cc: Borislav Petkov 

Acked-by: Borislav Petkov 

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Borislav Petkov 
On Wed, Jan 28, 2015 at 05:10:46PM +, Elliott, Robert (Server Storage) 
wrote:
> Should this patch series also add defines for the virtual 
> machine control data structure changes?
> 
> 1. Add the new VM-Execution Controls bit 21 as
> SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
> to arch/x86/include/asm/vmx.h.
> 
> 2. Add the new exit reason of 64 (0x41) as
>   EXIT_REASON_PCOMMIT  64
> to arch/x86/include/uapi/asm/vmx.h and (with a
> VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.
> 
> 3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.

These look like a separate patchset for kvm enablement to me.

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Ross Zwisler 
On Wed, 2015-01-28 at 18:21 +0100, Borislav Petkov wrote:
> On Wed, Jan 28, 2015 at 05:10:46PM +, Elliott, Robert (Server Storage) 
> wrote:
> > Should this patch series also add defines for the virtual 
> > machine control data structure changes?
> > 
> > 1. Add the new VM-Execution Controls bit 21 as
> > SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
> > to arch/x86/include/asm/vmx.h.
> > 
> > 2. Add the new exit reason of 64 (0x41) as
> > EXIT_REASON_PCOMMIT  64
> > to arch/x86/include/uapi/asm/vmx.h and (with a
> > VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.
> > 
> > 3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.
> 
> These look like a separate patchset for kvm enablement to me.

Agreed, I think they are a separate patch set.

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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Ross Zwisler 
On Wed, 2015-01-28 at 18:21 +0100, Borislav Petkov wrote:
 On Wed, Jan 28, 2015 at 05:10:46PM +, Elliott, Robert (Server Storage) 
 wrote:
  Should this patch series also add defines for the virtual 
  machine control data structure changes?
  
  1. Add the new VM-Execution Controls bit 21 as
  SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
  to arch/x86/include/asm/vmx.h.
  
  2. Add the new exit reason of 64 (0x41) as
  EXIT_REASON_PCOMMIT  64
  to arch/x86/include/uapi/asm/vmx.h and (with a
  VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.
  
  3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.
 
 These look like a separate patchset for kvm enablement to me.

Agreed, I think they are a separate patch set.

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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Borislav Petkov 
On Wed, Jan 28, 2015 at 05:10:46PM +, Elliott, Robert (Server Storage) 
wrote:
 Should this patch series also add defines for the virtual 
 machine control data structure changes?
 
 1. Add the new VM-Execution Controls bit 21 as
 SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
 to arch/x86/include/asm/vmx.h.
 
 2. Add the new exit reason of 64 (0x41) as
   EXIT_REASON_PCOMMIT  64
 to arch/x86/include/uapi/asm/vmx.h and (with a
 VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.
 
 3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.

These look like a separate patchset for kvm enablement to me.

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--
--
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Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Borislav Petkov 
On Tue, Jan 27, 2015 at 09:53:50AM -0700, Ross Zwisler wrote:
 Add support for the new pcommit (persistent commit) instruction.  This
 instruction was announced in the document Intel Architecture
 Instruction Set Extensions Programming Reference with reference number
 319433-022.
 
 https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
 
 The pcommit instruction ensures that data that has been flushed from the
 processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
 memory and is durable on the DIMM.  The primary use case for this is 
 persistent
 memory.
 
 This function shows how to properly use clwb/clflushopt/clflush and
 pcommit with appropriate fencing:

...

 This is still correct, but now you've got two fences separated by only a
 nop.  With the commit and the fence together in pcommit_sfence() you
 avoid the final unneeded fence.
 
 Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
 Cc: H Peter Anvin h.peter.an...@intel.com
 Cc: Ingo Molnar mi...@kernel.org
 Cc: Thomas Gleixner t...@linutronix.de
 Cc: Borislav Petkov b...@alien8.de

Acked-by: Borislav Petkov b...@suse.de

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
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RE: [PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-28 Thread Elliott, Robert (Server Storage) 


 -Original Message-
 From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
 ow...@vger.kernel.org] On Behalf Of Ross Zwisler
 Sent: Tuesday, 27 January, 2015 10:54 AM
 To: linux-kernel@vger.kernel.org
 Cc: Ross Zwisler; H Peter Anvin; Ingo Molnar; Thomas Gleixner; Borislav
 Petkov
 Subject: [PATCH v3 1/2] x86: Add support for the pcommit instruction
 
 Add support for the new pcommit (persistent commit) instruction.  This
 instruction was announced in the document Intel Architecture
 Instruction Set Extensions Programming Reference with reference number
 319433-022.
 
 https://software.intel.com/sites/default/files/managed/0d/53/319433-
 022.pdf
 
...
 ---
  arch/x86/include/asm/cpufeature.h| 1 +
  arch/x86/include/asm/special_insns.h | 8 
  2 files changed, 9 insertions(+)

Should this patch series also add defines for the virtual 
machine control data structure changes?

1. Add the new VM-Execution Controls bit 21 as
SECONDARY_EXEC_PCOMMIT_EXITING 0x0020
to arch/x86/include/asm/vmx.h.

2. Add the new exit reason of 64 (0x41) as
EXIT_REASON_PCOMMIT  64
to arch/x86/include/uapi/asm/vmx.h and (with a
VMX_EXIT_REASONS string) to usr/include/asm/vmx.h.

3. Add a kvm_vmx_exit_handler to arch/x86/kvm/vmx.c.


---
Rob ElliottHP Server Storage


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[PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-27 Thread Ross Zwisler 
Add support for the new pcommit (persistent commit) instruction.  This
instruction was announced in the document "Intel Architecture
Instruction Set Extensions Programming Reference" with reference number
319433-022.

https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf

The pcommit instruction ensures that data that has been flushed from the
processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
memory and is durable on the DIMM.  The primary use case for this is persistent
memory.

This function shows how to properly use clwb/clflushopt/clflush and
pcommit with appropriate fencing:

void flush_and_commit_buffer(void *vaddr, unsigned int size)
{
void *vend = vaddr + size - 1;

for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
clwb(vaddr);

/* Flush any possible final partial cacheline */
clwb(vend);

/*
 * sfence to order clwb/clflushopt/clflush cache flushes
 * mfence via mb() also works
 */
wmb();

/* pcommit and the required sfence for ordering */
pcommit_sfence();
}

After this function completes the data pointed to by vaddr is has been
accepted to memory and will be durable if the vaddr points to
persistent memory.

Pcommit must always be ordered by an mfence or sfence, so to help
simplify things we include both the pcommit and the required sfence in
the alternatives generated by pcommit_sfence().  The other option is to
keep them separated, but on platforms that don't support pcommit this
would then turn into:

void flush_and_commit_buffer(void *vaddr, unsigned int size)
{
void *vend = vaddr + size - 1;

for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
clwb(vaddr);

/* Flush any possible final partial cacheline */
clwb(vend);

/*
 * sfence to order clwb/clflushopt/clflush cache flushes
 * mfence via mb() also works
 */
wmb();

nop(); /* from pcommit(), via alternatives */

/*
 * sfence to order pcommit
 * mfence via mb() also works
 */
wmb();
}

This is still correct, but now you've got two fences separated by only a
nop.  With the commit and the fence together in pcommit_sfence() you
avoid the final unneeded fence.

Signed-off-by: Ross Zwisler 
Cc: H Peter Anvin 
Cc: Ingo Molnar 
Cc: Thomas Gleixner 
Cc: Borislav Petkov 
---
 arch/x86/include/asm/cpufeature.h| 1 +
 arch/x86/include/asm/special_insns.h | 8 
 2 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index bb9b258..dfdd689 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -220,6 +220,7 @@
 #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
 #define X86_FEATURE_ADX( 9*32+19) /* The ADCX and ADOX 
instructions */
 #define X86_FEATURE_SMAP   ( 9*32+20) /* Supervisor Mode Access Prevention 
*/
+#define X86_FEATURE_PCOMMIT( 9*32+22) /* PCOMMIT instruction */
 #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
 #define X86_FEATURE_AVX512PF   ( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER   ( 9*32+27) /* AVX-512 Exponential and 
Reciprocal */
diff --git a/arch/x86/include/asm/special_insns.h 
b/arch/x86/include/asm/special_insns.h
index e820c08..d686f9b 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -199,6 +199,14 @@ static inline void clflushopt(volatile void *__p)
   "+m" (*(volatile char __force *)__p));
 }
 
+static inline void pcommit_sfence(void)
+{
+   alternative(ASM_NOP7,
+   ".byte 0x66, 0x0f, 0xae, 0xf8\n\t" /* pcommit */
+   "sfence",
+   X86_FEATURE_PCOMMIT);
+}
+
 #define nop() asm volatile ("nop")
 
 
-- 
1.9.3

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[PATCH v3 1/2] x86: Add support for the pcommit instruction

2015-01-27 Thread Ross Zwisler 
Add support for the new pcommit (persistent commit) instruction.  This
instruction was announced in the document Intel Architecture
Instruction Set Extensions Programming Reference with reference number
319433-022.

https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf

The pcommit instruction ensures that data that has been flushed from the
processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
memory and is durable on the DIMM.  The primary use case for this is persistent
memory.

This function shows how to properly use clwb/clflushopt/clflush and
pcommit with appropriate fencing:

void flush_and_commit_buffer(void *vaddr, unsigned int size)
{
void *vend = vaddr + size - 1;

for (; vaddr  vend; vaddr += boot_cpu_data.x86_clflush_size)
clwb(vaddr);

/* Flush any possible final partial cacheline */
clwb(vend);

/*
 * sfence to order clwb/clflushopt/clflush cache flushes
 * mfence via mb() also works
 */
wmb();

/* pcommit and the required sfence for ordering */
pcommit_sfence();
}

After this function completes the data pointed to by vaddr is has been
accepted to memory and will be durable if the vaddr points to
persistent memory.

Pcommit must always be ordered by an mfence or sfence, so to help
simplify things we include both the pcommit and the required sfence in
the alternatives generated by pcommit_sfence().  The other option is to
keep them separated, but on platforms that don't support pcommit this
would then turn into:

void flush_and_commit_buffer(void *vaddr, unsigned int size)
{
void *vend = vaddr + size - 1;

for (; vaddr  vend; vaddr += boot_cpu_data.x86_clflush_size)
clwb(vaddr);

/* Flush any possible final partial cacheline */
clwb(vend);

/*
 * sfence to order clwb/clflushopt/clflush cache flushes
 * mfence via mb() also works
 */
wmb();

nop(); /* from pcommit(), via alternatives */

/*
 * sfence to order pcommit
 * mfence via mb() also works
 */
wmb();
}

This is still correct, but now you've got two fences separated by only a
nop.  With the commit and the fence together in pcommit_sfence() you
avoid the final unneeded fence.

Signed-off-by: Ross Zwisler ross.zwis...@linux.intel.com
Cc: H Peter Anvin h.peter.an...@intel.com
Cc: Ingo Molnar mi...@kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Borislav Petkov b...@alien8.de
---
 arch/x86/include/asm/cpufeature.h| 1 +
 arch/x86/include/asm/special_insns.h | 8 
 2 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index bb9b258..dfdd689 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -220,6 +220,7 @@
 #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
 #define X86_FEATURE_ADX( 9*32+19) /* The ADCX and ADOX 
instructions */
 #define X86_FEATURE_SMAP   ( 9*32+20) /* Supervisor Mode Access Prevention 
*/
+#define X86_FEATURE_PCOMMIT( 9*32+22) /* PCOMMIT instruction */
 #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
 #define X86_FEATURE_AVX512PF   ( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER   ( 9*32+27) /* AVX-512 Exponential and 
Reciprocal */
diff --git a/arch/x86/include/asm/special_insns.h 
b/arch/x86/include/asm/special_insns.h
index e820c08..d686f9b 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -199,6 +199,14 @@ static inline void clflushopt(volatile void *__p)
   +m (*(volatile char __force *)__p));
 }
 
+static inline void pcommit_sfence(void)
+{
+   alternative(ASM_NOP7,
+   .byte 0x66, 0x0f, 0xae, 0xf8\n\t /* pcommit */
+   sfence,
+   X86_FEATURE_PCOMMIT);
+}
+
 #define nop() asm volatile (nop)
 
 
-- 
1.9.3

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