On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
> Subject: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h
Did you ever notice that all patches have a subsystem related prefix before
the sentence decribing the change?
See Documentation/SubmittingPatches. Also git log some/file mi
On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
> Subject: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h
Did you ever notice that all patches have a subsystem related prefix before
the sentence decribing the change?
See Documentation/SubmittingPatches. Also git log some/file mi
Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
MISC_THD_FEATURE_ENABLE 0x140.
Setting its 2nd bit make MONITOR and MWAIT instructions do not cause
invalid-opcode exception.
This commit adds this register prefixed by PHI and bit to msr-info.h
Reference:
Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
MISC_THD_FEATURE_ENABLE 0x140.
Setting its 2nd bit make MONITOR and MWAIT instructions do not cause
invalid-opcode exception.
This commit adds this register prefixed by PHI and bit to msr-info.h
Reference:
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