Re: [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

On 09/21, Abhishek Sahu wrote: > diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c > index b2decd5..a2809db 100644 > --- a/drivers/clk/qcom/gcc-ipq4019.c > +++ b/drivers/clk/qcom/gcc-ipq4019.c > @@ -546,7 +546,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] =

[PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

The feedback divider for DDR PLL has been changed in IPQ4019 bootloader from 111 to 112 so changed the frequency values for the same. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/gcc-ipq4019.c | 52 +- 1 file changed, 26 insertions(+), 26 deletions(-)