[PATCH v4 07/10] ARM: dts: sun8i: a83t: Add CCI-400 node
Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Mylène Josserand--- arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 3eae3c27e04d..84d6c7738125 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -64,48 +64,56 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + cci-control-port = <_control0>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + cci-control-port = <_control0>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + cci-control-port = <_control0>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + cci-control-port = <_control0>; }; cpu@100 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x100>; + cci-control-port = <_control1>; }; cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x101>; + cci-control-port = <_control1>; }; cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x102>; + cci-control-port = <_control1>; }; cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x103>; + cci-control-port = <_control1>; }; }; @@ -236,6 +244,39 @@ reg = <0x0170 0x400>; }; + cci@179 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0179 0x1>; + ranges = <0x0 0x0179 0x1>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , +, +, +, +, +, +, +; + }; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; -- 2.11.0
[PATCH v4 07/10] ARM: dts: sun8i: a83t: Add CCI-400 node
Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Mylène Josserand --- arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 3eae3c27e04d..84d6c7738125 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -64,48 +64,56 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + cci-control-port = <_control0>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + cci-control-port = <_control0>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + cci-control-port = <_control0>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + cci-control-port = <_control0>; }; cpu@100 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x100>; + cci-control-port = <_control1>; }; cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x101>; + cci-control-port = <_control1>; }; cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x102>; + cci-control-port = <_control1>; }; cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0x103>; + cci-control-port = <_control1>; }; }; @@ -236,6 +244,39 @@ reg = <0x0170 0x400>; }; + cci@179 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0179 0x1>; + ranges = <0x0 0x0179 0x1>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , +, +, +, +, +, +, +; + }; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; -- 2.11.0