[PATCH v4 1/4] x86/phi: Add R3MWAIT register and bit to msr-info.h

Intel Xeon Phi x200 (codenamed Knights Landing) has MSR MISC_THD_FEATURE_ENABLE 0x140. Setting 2nd bit of this register makes MONITOR and MWAIT instructions do not cause invalid-opcode exception when called from ring different than 0. Hex Dec NameScope 140H 320

[PATCH v4 1/4] x86/phi: Add R3MWAIT register and bit to msr-info.h

Intel Xeon Phi x200 (codenamed Knights Landing) has MSR MISC_THD_FEATURE_ENABLE 0x140. Setting 2nd bit of this register makes MONITOR and MWAIT instructions do not cause invalid-opcode exception when called from ring different than 0. Hex Dec NameScope 140H 320