[PATCH v4 16/22] arm64: capabilities: Clean up midr range helpers

[Suzuki K Poulose]

We are about to introduce generic MIDR range helpers. Clean
up the existing helpers in erratum handling, preparing them
to use generic version.

Cc: Will Deacon 
Cc: Mark Rutland 
Cc: Ard Biesheuvel 
Reviewed-by: Dave Martin 
Signed-off-by: Suzuki K Poulose 
---
 arch/arm64/kernel/cpu_errata.c | 106 +++--
 1 file changed, 59 insertions(+), 47 deletions(-)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index f5ab9545c5ea..9ea14954972c 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -237,23 +237,38 @@ qcom_enable_link_stack_sanitization(const struct 
arm64_cpu_capabilities *entry)
 }
 #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 
-#define MIDR_RANGE(model, min, max) \
-   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
-   .matches = is_affected_midr_range, \
-   .midr_model = model, \
-   .midr_range_min = min, \
-   .midr_range_max = max
+#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)  \
+   .matches = is_affected_midr_range,  \
+   .midr_model = model,\
+   .midr_range_min = MIDR_CPU_VAR_REV(v_min, r_min),   \
+   .midr_range_max = MIDR_CPU_VAR_REV(v_max, r_max)
 
-#define MIDR_ALL_VERSIONS(model) \
-   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
-   .matches = is_affected_midr_range, \
-   .midr_model = model, \
-   .midr_range_min = 0, \
+#define CAP_MIDR_ALL_VERSIONS(model)   \
+   .matches = is_affected_midr_range,  \
+   .midr_model = model,\
+   .midr_range_min = MIDR_CPU_VAR_REV(0, 0),   \
.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
 
 #define MIDR_FIXED(rev, revidr_mask) \
.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 
+#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)   \
+   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+   CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
+
+/* Errata affecting a range of revisions of  given model variant */
+#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
+   ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
+
+/* Errata affecting a single variant/revision of a model */
+#define ERRATA_MIDR_REV(model, var, rev)   \
+   ERRATA_MIDR_RANGE(model, var, rev, var, rev)
+
+/* Errata affecting all variants/revisions of a given a model */
+#define ERRATA_MIDR_ALL_VERSIONS(model)\
+   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+   CAP_MIDR_ALL_VERSIONS(model)
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdefined(CONFIG_ARM64_ERRATUM_826319) || \
defined(CONFIG_ARM64_ERRATUM_827319) || \
@@ -262,7 +277,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[012] */
.desc = "ARM errata 826319, 827319, 824069",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
-   MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
+   ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
.cpu_enable = cpu_enable_cache_maint_trap,
},
 #endif
@@ -271,7 +286,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[01] */
.desc = "ARM errata 819472",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
-   MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
+   ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
.cpu_enable = cpu_enable_cache_maint_trap,
},
 #endif
@@ -280,9 +295,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 832075",
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
-   MIDR_RANGE(MIDR_CORTEX_A57,
-  MIDR_CPU_VAR_REV(0, 0),
-  MIDR_CPU_VAR_REV(1, 2)),
+   ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_834220
@@ -290,9 +305,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 834220",
.capability = ARM64_WORKAROUND_834220,
-   MIDR_RANGE(MIDR_CORTEX_A57,
-  MIDR_CPU_VAR_REV(0, 0),
-  MIDR_CPU_VAR_REV(1, 2)),
+   ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_843419
@@ 

[PATCH v4 16/22] arm64: capabilities: Clean up midr range helpers

[Suzuki K Poulose]

We are about to introduce generic MIDR range helpers. Clean
up the existing helpers in erratum handling, preparing them
to use generic version.

Cc: Will Deacon 
Cc: Mark Rutland 
Cc: Ard Biesheuvel 
Reviewed-by: Dave Martin 
Signed-off-by: Suzuki K Poulose 
---
 arch/arm64/kernel/cpu_errata.c | 106 +++--
 1 file changed, 59 insertions(+), 47 deletions(-)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index f5ab9545c5ea..9ea14954972c 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -237,23 +237,38 @@ qcom_enable_link_stack_sanitization(const struct 
arm64_cpu_capabilities *entry)
 }
 #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 
-#define MIDR_RANGE(model, min, max) \
-   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
-   .matches = is_affected_midr_range, \
-   .midr_model = model, \
-   .midr_range_min = min, \
-   .midr_range_max = max
+#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)  \
+   .matches = is_affected_midr_range,  \
+   .midr_model = model,\
+   .midr_range_min = MIDR_CPU_VAR_REV(v_min, r_min),   \
+   .midr_range_max = MIDR_CPU_VAR_REV(v_max, r_max)
 
-#define MIDR_ALL_VERSIONS(model) \
-   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
-   .matches = is_affected_midr_range, \
-   .midr_model = model, \
-   .midr_range_min = 0, \
+#define CAP_MIDR_ALL_VERSIONS(model)   \
+   .matches = is_affected_midr_range,  \
+   .midr_model = model,\
+   .midr_range_min = MIDR_CPU_VAR_REV(0, 0),   \
.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
 
 #define MIDR_FIXED(rev, revidr_mask) \
.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 
+#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)   \
+   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+   CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
+
+/* Errata affecting a range of revisions of  given model variant */
+#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
+   ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
+
+/* Errata affecting a single variant/revision of a model */
+#define ERRATA_MIDR_REV(model, var, rev)   \
+   ERRATA_MIDR_RANGE(model, var, rev, var, rev)
+
+/* Errata affecting all variants/revisions of a given a model */
+#define ERRATA_MIDR_ALL_VERSIONS(model)\
+   .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+   CAP_MIDR_ALL_VERSIONS(model)
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdefined(CONFIG_ARM64_ERRATUM_826319) || \
defined(CONFIG_ARM64_ERRATUM_827319) || \
@@ -262,7 +277,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[012] */
.desc = "ARM errata 826319, 827319, 824069",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
-   MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
+   ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
.cpu_enable = cpu_enable_cache_maint_trap,
},
 #endif
@@ -271,7 +286,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[01] */
.desc = "ARM errata 819472",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
-   MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
+   ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
.cpu_enable = cpu_enable_cache_maint_trap,
},
 #endif
@@ -280,9 +295,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 832075",
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
-   MIDR_RANGE(MIDR_CORTEX_A57,
-  MIDR_CPU_VAR_REV(0, 0),
-  MIDR_CPU_VAR_REV(1, 2)),
+   ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_834220
@@ -290,9 +305,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 834220",
.capability = ARM64_WORKAROUND_834220,
-   MIDR_RANGE(MIDR_CORTEX_A57,
-  MIDR_CPU_VAR_REV(0, 0),
-  MIDR_CPU_VAR_REV(1, 2)),
+   ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_843419
@@ -300,7 +315,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[01234] */