Use standard V4L2 control to get pixel clock rate from a sensor
linked in the media controller pipeline. Then calculate clock
rates on CSIPHY, CSID and VFE to use the lowest possible.
If the currnet pixel clock rate of the sensor cannot be read then
use the highest possible. This case covers also
Use standard V4L2 control to get pixel clock rate from a sensor
linked in the media controller pipeline. Then calculate clock
rates on CSIPHY, CSID and VFE to use the lowest possible.
If the currnet pixel clock rate of the sensor cannot be read then
use the highest possible. This case covers also
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