[PATCH v4 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

[Suzuki K Poulose]

This patch documents the devicetree bindings for ARM DSU PMU.

Cc: Mark Rutland 
Cc: Will Deacon 
Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Cc: frowand.l...@gmail.com
Signed-off-by: Suzuki K Poulose 
---
Changes since V3:
 - Fixed node name in the example, suggested by Rob
---
 .../devicetree/bindings/arm/arm-dsu-pmu.txt| 27 ++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt 
b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
new file mode 100644
index 000..6efabba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
@@ -0,0 +1,27 @@
+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+
+** DSU PMU required properties:
+
+- compatible   : should be one of :
+
+   "arm,dsu-pmu"
+
+- interrupts   : Exactly 1 SPI must be listed.
+
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+
+
+** Example:
+
+dsu-pmu-0 {
+   compatible = "arm,dsu-pmu";
+   interrupts = ;
+   cpus = <_0>, <_1>;
+};
-- 
2.7.5

[PATCH v4 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

[Suzuki K Poulose]

This patch documents the devicetree bindings for ARM DSU PMU.

Cc: Mark Rutland 
Cc: Will Deacon 
Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Cc: frowand.l...@gmail.com
Signed-off-by: Suzuki K Poulose 
---
Changes since V3:
 - Fixed node name in the example, suggested by Rob
---
 .../devicetree/bindings/arm/arm-dsu-pmu.txt| 27 ++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt 
b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
new file mode 100644
index 000..6efabba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
@@ -0,0 +1,27 @@
+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+
+** DSU PMU required properties:
+
+- compatible   : should be one of :
+
+   "arm,dsu-pmu"
+
+- interrupts   : Exactly 1 SPI must be listed.
+
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+
+
+** Example:
+
+dsu-pmu-0 {
+   compatible = "arm,dsu-pmu";
+   interrupts = ;
+   cpus = <_0>, <_1>;
+};
-- 
2.7.5