Re: [PATCH v4 6/6] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623
On 03/06/2018 10:09 AM, Ryder Lee wrote: > Modify audio related nodes to reflect the actual usage in binding documents. > > Signed-off-by: Ryder Lee > --- applied to v4.17-next/dts32 Thanks! > arch/arm/boot/dts/mt2701.dtsi | 188 - > arch/arm/boot/dts/mt7623.dtsi | 190 > -- > 2 files changed, 182 insertions(+), 196 deletions(-) > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi > index 05557fc..05cf65c 100644 > --- a/arch/arm/boot/dts/mt2701.dtsi > +++ b/arch/arm/boot/dts/mt2701.dtsi > @@ -426,104 +426,96 @@ > status = "disabled"; > }; > > - afe: audio-controller@1122 { > - compatible = "mediatek,mt2701-audio"; > - reg = <0 0x1122 0 0x2000>, > - <0 0x112a 0 0x2>; > - interrupts = , > - ; > - interrupt-names = "afe", "asys"; > - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; > - > - clocks = <&infracfg CLK_INFRA_AUDIO>, > - <&topckgen CLK_TOP_AUD_MUX1_SEL>, > - <&topckgen CLK_TOP_AUD_MUX2_SEL>, > - <&topckgen CLK_TOP_AUD_MUX1_DIV>, > - <&topckgen CLK_TOP_AUD_MUX2_DIV>, > - <&topckgen CLK_TOP_AUD_48K_TIMING>, > - <&topckgen CLK_TOP_AUD_44K_TIMING>, > - <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, > - <&topckgen CLK_TOP_APLL_SEL>, > - <&topckgen CLK_TOP_AUD1PLL_98M>, > - <&topckgen CLK_TOP_AUD2PLL_90M>, > - <&topckgen CLK_TOP_HADDS2PLL_98M>, > - <&topckgen CLK_TOP_HADDS2PLL_294M>, > - <&topckgen CLK_TOP_AUDPLL>, > - <&topckgen CLK_TOP_AUDPLL_D4>, > - <&topckgen CLK_TOP_AUDPLL_D8>, > - <&topckgen CLK_TOP_AUDPLL_D16>, > - <&topckgen CLK_TOP_AUDPLL_D24>, > - <&topckgen CLK_TOP_AUDINTBUS_SEL>, > - <&clk26m>, > - <&topckgen CLK_TOP_SYSPLL1_D4>, > - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, > - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, > - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, > - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, > - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, > - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, > - <&topckgen CLK_TOP_AUD_I2S5_MCLK>, > - <&topckgen CLK_TOP_AUD_I2S6_MCLK>, > - <&topckgen CLK_TOP_ASM_M_SEL>, > - <&topckgen CLK_TOP_ASM_H_SEL>, > - <&topckgen CLK_TOP_UNIVPLL2_D4>, > - <&topckgen CLK_TOP_UNIVPLL2_D2>, > - <&topckgen CLK_TOP_SYSPLL_D5>; > - > - clock-names = "infra_sys_audio_clk", > - "top_audio_mux1_sel", > - "top_audio_mux2_sel", > - "top_audio_mux1_div", > - "top_audio_mux2_div", > - "top_audio_48k_timing", > - "top_audio_44k_timing", > - "top_audpll_mux_sel", > - "top_apll_sel", > - "top_aud1_pll_98M", > - "top_aud2_pll_90M", > - "top_hadds2_pll_98M", > - "top_hadds2_pll_294M", > - "top_audpll", > - "top_audpll_d4", > - "top_audpll_d8", > - "top_audpll_d16", > - "top_audpll_d24", > - "top_audintbus_sel", > - "clk_26m", > - "top_syspll1_d4", > - "top_aud_k1_src_sel", > - "top_aud_k2_src_sel", > - "top_aud_k3_src_sel", > - "top_aud_k4_src_sel", > - "top_aud_k5_src_sel", > - "top_aud_k6_src_sel", > - "top_aud_k1_src_div", > - "top_aud_k2_src_div", > - "top_aud_k3_
[PATCH v4 6/6] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623
Modify audio related nodes to reflect the actual usage in binding documents. Signed-off-by: Ryder Lee --- arch/arm/boot/dts/mt2701.dtsi | 188 - arch/arm/boot/dts/mt7623.dtsi | 190 -- 2 files changed, 182 insertions(+), 196 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 05557fc..05cf65c 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -426,104 +426,96 @@ status = "disabled"; }; - afe: audio-controller@1122 { - compatible = "mediatek,mt2701-audio"; - reg = <0 0x1122 0 0x2000>, - <0 0x112a 0 0x2>; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, -<&topckgen CLK_TOP_AUD_MUX1_SEL>, -<&topckgen CLK_TOP_AUD_MUX2_SEL>, -<&topckgen CLK_TOP_AUD_MUX1_DIV>, -<&topckgen CLK_TOP_AUD_MUX2_DIV>, -<&topckgen CLK_TOP_AUD_48K_TIMING>, -<&topckgen CLK_TOP_AUD_44K_TIMING>, -<&topckgen CLK_TOP_AUDPLL_MUX_SEL>, -<&topckgen CLK_TOP_APLL_SEL>, -<&topckgen CLK_TOP_AUD1PLL_98M>, -<&topckgen CLK_TOP_AUD2PLL_90M>, -<&topckgen CLK_TOP_HADDS2PLL_98M>, -<&topckgen CLK_TOP_HADDS2PLL_294M>, -<&topckgen CLK_TOP_AUDPLL>, -<&topckgen CLK_TOP_AUDPLL_D4>, -<&topckgen CLK_TOP_AUDPLL_D8>, -<&topckgen CLK_TOP_AUDPLL_D16>, -<&topckgen CLK_TOP_AUDPLL_D24>, -<&topckgen CLK_TOP_AUDINTBUS_SEL>, -<&clk26m>, -<&topckgen CLK_TOP_SYSPLL1_D4>, -<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K5_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K6_SRC_SEL>, -<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, -<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, -<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, -<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, -<&topckgen CLK_TOP_AUD_K5_SRC_DIV>, -<&topckgen CLK_TOP_AUD_K6_SRC_DIV>, -<&topckgen CLK_TOP_AUD_I2S1_MCLK>, -<&topckgen CLK_TOP_AUD_I2S2_MCLK>, -<&topckgen CLK_TOP_AUD_I2S3_MCLK>, -<&topckgen CLK_TOP_AUD_I2S4_MCLK>, -<&topckgen CLK_TOP_AUD_I2S5_MCLK>, -<&topckgen CLK_TOP_AUD_I2S6_MCLK>, -<&topckgen CLK_TOP_ASM_M_SEL>, -<&topckgen CLK_TOP_ASM_H_SEL>, -<&topckgen CLK_TOP_UNIVPLL2_D4>, -<&topckgen CLK_TOP_UNIVPLL2_D2>, -<&topckgen CLK_TOP_SYSPLL_D5>; - - clock-names = "infra_sys_audio_clk", -"top_audio_mux1_sel", -"top_audio_mux2_sel", -"top_audio_mux1_div", -"top_audio_mux2_div", -"top_audio_48k_timing", -"top_audio_44k_timing", -"top_audpll_mux_sel", -"top_apll_sel", -"top_aud1_pll_98M", -"top_aud2_pll_90M", -"top_hadds2_pll_98M", -"top_hadds2_pll_294M", -"top_audpll", -"top_audpll_d4", -"top_audpll_d8", -"top_audpll_d16", -"top_audpll_d24", -"top_audintbus_sel", -"clk_26m", -"top_syspll1_d4", -"top_aud_k1_src_sel", -"top_aud_k2_src_sel", -"top_aud_k3_src_sel", -"top_aud_k4_src_sel", -"top_aud_k5_src_sel", -"top_aud_k6_src_sel", -"top_aud_k1_src_div", -"top_aud_k2_src_div", -"top_aud_k3_src_div", -"top_aud_k4_src_div", -"top_aud_k5_src_div", -