Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-18 Thread Mark Rutland
On Fri, Aug 18, 2017 at 11:43:32AM +0100, Suzuki K Poulose wrote: > On 17/08/17 16:57, Mark Rutland wrote: > >On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote: > >>On 16/08/17 15:10, Mark Rutland wrote: > >>>On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: > +s

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-18 Thread Suzuki K Poulose
On 17/08/17 16:57, Mark Rutland wrote: On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote: On 16/08/17 15:10, Mark Rutland wrote: On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: +static struct attribute *dsu_pmu_event_attrs[] = { + DSU_EVENT_ATTR(cycles,

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-17 Thread Mark Rutland
On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote: > On 16/08/17 15:10, Mark Rutland wrote: > >On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: > >>+static struct attribute *dsu_pmu_event_attrs[] = { > >>+ DSU_EVENT_ATTR(cycles, 0x11), > >>+ DSU_EVENT_ATTR(bus_a

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-17 Thread Suzuki K Poulose
Hi Mark, On 16/08/17 15:10, Mark Rutland wrote: On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: +/* + * struct dsu_pmu - DSU PMU descriptor + * + * @pmu_lock : Protects accesses to DSU PMU register from multiple + * CPUs. + * @hw_events

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-16 Thread Mark Rutland
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: > +/* > + * struct dsu_pmu- DSU PMU descriptor > + * > + * @pmu_lock : Protects accesses to DSU PMU register from multiple > + * CPUs. > + * @hw_events: Holds the event counter state. >

[PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

2017-08-08 Thread Suzuki K Poulose
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The PMU allows counting the various events related to L3, SCU etc, along with providing a cyc