On Fri, Aug 18, 2017 at 11:43:32AM +0100, Suzuki K Poulose wrote:
> On 17/08/17 16:57, Mark Rutland wrote:
> >On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote:
> >>On 16/08/17 15:10, Mark Rutland wrote:
> >>>On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
> +s
On 17/08/17 16:57, Mark Rutland wrote:
On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote:
On 16/08/17 15:10, Mark Rutland wrote:
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
+static struct attribute *dsu_pmu_event_attrs[] = {
+ DSU_EVENT_ATTR(cycles,
On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote:
> On 16/08/17 15:10, Mark Rutland wrote:
> >On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
> >>+static struct attribute *dsu_pmu_event_attrs[] = {
> >>+ DSU_EVENT_ATTR(cycles, 0x11),
> >>+ DSU_EVENT_ATTR(bus_a
Hi Mark,
On 16/08/17 15:10, Mark Rutland wrote:
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
+/*
+ * struct dsu_pmu - DSU PMU descriptor
+ *
+ * @pmu_lock : Protects accesses to DSU PMU register from multiple
+ * CPUs.
+ * @hw_events
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
> +/*
> + * struct dsu_pmu- DSU PMU descriptor
> + *
> + * @pmu_lock : Protects accesses to DSU PMU register from multiple
> + * CPUs.
> + * @hw_events: Holds the event counter state.
>
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic, and external interfaces to form a multicore cluster. The PMU
allows counting the various events related to L3, SCU etc, along with
providing a cyc
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