Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Lina Iyer 

On Thu, Feb 15 2018 at 20:24 +, Thomas Gleixner wrote:

On Thu, 15 Feb 2018, Lina Iyer wrote:

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:
> On Fri, 9 Feb 2018, Lina Iyer wrote:
> > +enum pdc_irq_config_bits {
> > + PDC_POLARITY_LOW= 0,
> > + PDC_FALLING_EDGE= 2,
> > + PDC_POLARITY_HIGH   = 4,
> > + PDC_RISING_EDGE = 6,
> > + PDC_DUAL_EDGE   = 7,
>
> My previous comment about using binary constants still stands. Please
> either address review comments or reply at least. Ignoring reviews is not
> an option.
>
> Aside of that I really have to ask about the naming of these constants. Are
> these names hardware register nomenclature? If yes, they are disgusting. If
> no, they are still disgusting, but should be changed to sensible ones,
> which just match the IRQ_TYPE naming convention.
>
>PDC_LEVEL_LOW   = 000b,
>PDC_EDGE_FALLING= 010b,
>
>
>
Checkpatch doesn't like binary constants. I guess I will need to keep
the enum definitions in hex or decimal. I will remove the binary from
the comments though.


Well checkpatch is not always right.



commit 95e2c6023b0e4c8499fb521697f79215f69135fe
Author: Joe Perches 
Date:   Wed Jul 3 15:05:20 2013 -0700

   checkpatch: warn when using gcc's binary constant ("0b") extension

   The gcc extension for binary constants that start with 0b is only
   supported with gcc version 4.3 or higher.


Can anything of this be compiled with gcc < 4.3?


I don't see a reason why this would be compiled with a older GCC. I am
okay with ignoring the checkpatch errors. I was just not sure if I
should.

Thanks,
Lina

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Lina Iyer 

On Thu, Feb 15 2018 at 20:24 +, Thomas Gleixner wrote:

On Thu, 15 Feb 2018, Lina Iyer wrote:

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:
> On Fri, 9 Feb 2018, Lina Iyer wrote:
> > +enum pdc_irq_config_bits {
> > + PDC_POLARITY_LOW= 0,
> > + PDC_FALLING_EDGE= 2,
> > + PDC_POLARITY_HIGH   = 4,
> > + PDC_RISING_EDGE = 6,
> > + PDC_DUAL_EDGE   = 7,
>
> My previous comment about using binary constants still stands. Please
> either address review comments or reply at least. Ignoring reviews is not
> an option.
>
> Aside of that I really have to ask about the naming of these constants. Are
> these names hardware register nomenclature? If yes, they are disgusting. If
> no, they are still disgusting, but should be changed to sensible ones,
> which just match the IRQ_TYPE naming convention.
>
>PDC_LEVEL_LOW   = 000b,
>PDC_EDGE_FALLING= 010b,
>
>
>
Checkpatch doesn't like binary constants. I guess I will need to keep
the enum definitions in hex or decimal. I will remove the binary from
the comments though.


Well checkpatch is not always right.



commit 95e2c6023b0e4c8499fb521697f79215f69135fe
Author: Joe Perches 
Date:   Wed Jul 3 15:05:20 2013 -0700

   checkpatch: warn when using gcc's binary constant ("0b") extension

   The gcc extension for binary constants that start with 0b is only
   supported with gcc version 4.3 or higher.


Can anything of this be compiled with gcc < 4.3?


I don't see a reason why this would be compiled with a older GCC. I am
okay with ignoring the checkpatch errors. I was just not sure if I
should.

Thanks,
Lina

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Thomas Gleixner 
On Thu, 15 Feb 2018, Lina Iyer wrote:
> On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:
> > On Fri, 9 Feb 2018, Lina Iyer wrote:
> > > +enum pdc_irq_config_bits {
> > > + PDC_POLARITY_LOW= 0,
> > > + PDC_FALLING_EDGE= 2,
> > > + PDC_POLARITY_HIGH   = 4,
> > > + PDC_RISING_EDGE = 6,
> > > + PDC_DUAL_EDGE   = 7,
> > 
> > My previous comment about using binary constants still stands. Please
> > either address review comments or reply at least. Ignoring reviews is not
> > an option.
> > 
> > Aside of that I really have to ask about the naming of these constants. Are
> > these names hardware register nomenclature? If yes, they are disgusting. If
> > no, they are still disgusting, but should be changed to sensible ones,
> > which just match the IRQ_TYPE naming convention.
> > 
> >PDC_LEVEL_LOW= 000b,
> >PDC_EDGE_FALLING = 010b,
> >
> > 
> > 
> Checkpatch doesn't like binary constants. I guess I will need to keep
> the enum definitions in hex or decimal. I will remove the binary from
> the comments though.

Well checkpatch is not always right.

> 
> commit 95e2c6023b0e4c8499fb521697f79215f69135fe
> Author: Joe Perches 
> Date:   Wed Jul 3 15:05:20 2013 -0700
> 
>checkpatch: warn when using gcc's binary constant ("0b") extension
> 
>The gcc extension for binary constants that start with 0b is only
>supported with gcc version 4.3 or higher.

Can anything of this be compiled with gcc < 4.3?  

Thanks,

tglx

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Thomas Gleixner 
On Thu, 15 Feb 2018, Lina Iyer wrote:
> On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:
> > On Fri, 9 Feb 2018, Lina Iyer wrote:
> > > +enum pdc_irq_config_bits {
> > > + PDC_POLARITY_LOW= 0,
> > > + PDC_FALLING_EDGE= 2,
> > > + PDC_POLARITY_HIGH   = 4,
> > > + PDC_RISING_EDGE = 6,
> > > + PDC_DUAL_EDGE   = 7,
> > 
> > My previous comment about using binary constants still stands. Please
> > either address review comments or reply at least. Ignoring reviews is not
> > an option.
> > 
> > Aside of that I really have to ask about the naming of these constants. Are
> > these names hardware register nomenclature? If yes, they are disgusting. If
> > no, they are still disgusting, but should be changed to sensible ones,
> > which just match the IRQ_TYPE naming convention.
> > 
> >PDC_LEVEL_LOW= 000b,
> >PDC_EDGE_FALLING = 010b,
> >
> > 
> > 
> Checkpatch doesn't like binary constants. I guess I will need to keep
> the enum definitions in hex or decimal. I will remove the binary from
> the comments though.

Well checkpatch is not always right.

> 
> commit 95e2c6023b0e4c8499fb521697f79215f69135fe
> Author: Joe Perches 
> Date:   Wed Jul 3 15:05:20 2013 -0700
> 
>checkpatch: warn when using gcc's binary constant ("0b") extension
> 
>The gcc extension for binary constants that start with 0b is only
>supported with gcc version 4.3 or higher.

Can anything of this be compiled with gcc < 4.3?  

Thanks,

tglx

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Lina Iyer 

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:

On Fri, 9 Feb 2018, Lina Iyer wrote:

+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,


My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.

Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

   PDC_LEVEL_LOW= 000b,
   PDC_EDGE_FALLING = 010b,
   



Checkpatch doesn't like binary constants. I guess I will need to keep
the enum definitions in hex or decimal. I will remove the binary from
the comments though.

commit 95e2c6023b0e4c8499fb521697f79215f69135fe
Author: Joe Perches 
Date:   Wed Jul 3 15:05:20 2013 -0700

   checkpatch: warn when using gcc's binary constant ("0b") extension

   The gcc extension for binary constants that start with 0b is only
   supported with gcc version 4.3 or higher.

   The kernel can still be compiled with earlier versions of gcc, so have
   checkpatch emit a warning for these constants.

   Restructure checkpatch's constant finding code a bit to support finding
   these binary constants.

   Signed-off-by: Joe Perches 
   Suggested-by: Andrew Morton 
   Cc: Andy Whitcroft 
   Signed-off-by: Andrew Morton 
   Signed-off-by: Linus Torvalds 


Thanks,
Lina

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-15 Thread Lina Iyer 

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:

On Fri, 9 Feb 2018, Lina Iyer wrote:

+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,


My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.

Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

   PDC_LEVEL_LOW= 000b,
   PDC_EDGE_FALLING = 010b,
   



Checkpatch doesn't like binary constants. I guess I will need to keep
the enum definitions in hex or decimal. I will remove the binary from
the comments though.

commit 95e2c6023b0e4c8499fb521697f79215f69135fe
Author: Joe Perches 
Date:   Wed Jul 3 15:05:20 2013 -0700

   checkpatch: warn when using gcc's binary constant ("0b") extension

   The gcc extension for binary constants that start with 0b is only
   supported with gcc version 4.3 or higher.

   The kernel can still be compiled with earlier versions of gcc, so have
   checkpatch emit a warning for these constants.

   Restructure checkpatch's constant finding code a bit to support finding
   these binary constants.

   Signed-off-by: Joe Perches 
   Suggested-by: Andrew Morton 
   Cc: Andy Whitcroft 
   Signed-off-by: Andrew Morton 
   Signed-off-by: Linus Torvalds 


Thanks,
Lina

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-12 Thread Lina Iyer 

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:

On Fri, 9 Feb 2018, Lina Iyer wrote:

+/*
+ * GIC does not handle falling edge or active low. To allow falling edge and
+ * active low interrupts to be handled at GIC, PDC has an inverter that inverts
+ * falling edge into a rising edge and active low into an active high.
+ * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
+ * set as per the table below.
+ * (polarity, falling edge, rising edge ) POLARITY
+ * 3'b0 00  Level sensitive active lowLOW
+ * 3'b0 01  Rising edge sensitive NOT USED
+ * 3'b0 10  Falling edge sensitiveLOW
+ * 3'b0 11  Dual Edge sensitive   NOT USED
+ * 3'b1 00  Level sensitive active High   HIGH
+ * 3'b1 01  Falling Edge sensitiveNOT USED
+ * 3'b1 10  Rising edge sensitive HIGH
+ * 3'b1 11  Dual Edge sensitive   HIGH
+ */
+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,


My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.


I removed them from the enum definitions. Will remove them from the
comments as well. Sorry. It was not my intention to ignore any review
comments.


Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

   PDC_LEVEL_LOW= 000b,
   PDC_EDGE_FALLING = 010b,
   



They are named that way in spec :) Will change.


+   switch (type) {
+   case IRQ_TYPE_EDGE_RISING:
+   pdc_type = PDC_RISING_EDGE;
+   type = IRQ_TYPE_EDGE_RISING;


Whats the point of assigning the same value again?


Failed to notice. Will fix.

Thanks,
Lina


+   break;
+   case IRQ_TYPE_EDGE_FALLING:
+   pdc_type = PDC_FALLING_EDGE;
+   type = IRQ_TYPE_EDGE_RISING;
+   break;
+   case IRQ_TYPE_EDGE_BOTH:
+   pdc_type = PDC_DUAL_EDGE;
+   break;
+   case IRQ_TYPE_LEVEL_HIGH:
+   pdc_type = PDC_POLARITY_HIGH;
+   type = IRQ_TYPE_LEVEL_HIGH;


Ditto

Thanks,

tglx

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-12 Thread Lina Iyer 

On Mon, Feb 12 2018 at 13:40 +, Thomas Gleixner wrote:

On Fri, 9 Feb 2018, Lina Iyer wrote:

+/*
+ * GIC does not handle falling edge or active low. To allow falling edge and
+ * active low interrupts to be handled at GIC, PDC has an inverter that inverts
+ * falling edge into a rising edge and active low into an active high.
+ * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
+ * set as per the table below.
+ * (polarity, falling edge, rising edge ) POLARITY
+ * 3'b0 00  Level sensitive active lowLOW
+ * 3'b0 01  Rising edge sensitive NOT USED
+ * 3'b0 10  Falling edge sensitiveLOW
+ * 3'b0 11  Dual Edge sensitive   NOT USED
+ * 3'b1 00  Level sensitive active High   HIGH
+ * 3'b1 01  Falling Edge sensitiveNOT USED
+ * 3'b1 10  Rising edge sensitive HIGH
+ * 3'b1 11  Dual Edge sensitive   HIGH
+ */
+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,


My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.


I removed them from the enum definitions. Will remove them from the
comments as well. Sorry. It was not my intention to ignore any review
comments.


Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

   PDC_LEVEL_LOW= 000b,
   PDC_EDGE_FALLING = 010b,
   



They are named that way in spec :) Will change.


+   switch (type) {
+   case IRQ_TYPE_EDGE_RISING:
+   pdc_type = PDC_RISING_EDGE;
+   type = IRQ_TYPE_EDGE_RISING;


Whats the point of assigning the same value again?


Failed to notice. Will fix.

Thanks,
Lina


+   break;
+   case IRQ_TYPE_EDGE_FALLING:
+   pdc_type = PDC_FALLING_EDGE;
+   type = IRQ_TYPE_EDGE_RISING;
+   break;
+   case IRQ_TYPE_EDGE_BOTH:
+   pdc_type = PDC_DUAL_EDGE;
+   break;
+   case IRQ_TYPE_LEVEL_HIGH:
+   pdc_type = PDC_POLARITY_HIGH;
+   type = IRQ_TYPE_LEVEL_HIGH;


Ditto

Thanks,

tglx

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-12 Thread Thomas Gleixner 
On Fri, 9 Feb 2018, Lina Iyer wrote:
> +/*
> + * GIC does not handle falling edge or active low. To allow falling edge and
> + * active low interrupts to be handled at GIC, PDC has an inverter that 
> inverts
> + * falling edge into a rising edge and active low into an active high.
> + * For the inverter to work, the polarity bit in the IRQ_CONFIG register has 
> to
> + * set as per the table below.
> + * (polarity, falling edge, rising edge ) POLARITY
> + * 3'b0 00  Level sensitive active lowLOW
> + * 3'b0 01  Rising edge sensitive NOT USED
> + * 3'b0 10  Falling edge sensitiveLOW
> + * 3'b0 11  Dual Edge sensitive   NOT USED
> + * 3'b1 00  Level sensitive active High   HIGH
> + * 3'b1 01  Falling Edge sensitiveNOT USED
> + * 3'b1 10  Rising edge sensitive HIGH
> + * 3'b1 11  Dual Edge sensitive   HIGH
> + */
> +enum pdc_irq_config_bits {
> + PDC_POLARITY_LOW= 0,
> + PDC_FALLING_EDGE= 2,
> + PDC_POLARITY_HIGH   = 4,
> + PDC_RISING_EDGE = 6,
> + PDC_DUAL_EDGE   = 7,

My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.

Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

PDC_LEVEL_LOW   = 000b,
PDC_EDGE_FALLING= 010b,



> + switch (type) {
> + case IRQ_TYPE_EDGE_RISING:
> + pdc_type = PDC_RISING_EDGE;
> + type = IRQ_TYPE_EDGE_RISING;

Whats the point of assigning the same value again?

> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + pdc_type = PDC_FALLING_EDGE;
> + type = IRQ_TYPE_EDGE_RISING;
> + break;
> + case IRQ_TYPE_EDGE_BOTH:
> + pdc_type = PDC_DUAL_EDGE;
> + break;
> + case IRQ_TYPE_LEVEL_HIGH:
> + pdc_type = PDC_POLARITY_HIGH;
> + type = IRQ_TYPE_LEVEL_HIGH;

Ditto

Thanks,

tglx

Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-12 Thread Thomas Gleixner 
On Fri, 9 Feb 2018, Lina Iyer wrote:
> +/*
> + * GIC does not handle falling edge or active low. To allow falling edge and
> + * active low interrupts to be handled at GIC, PDC has an inverter that 
> inverts
> + * falling edge into a rising edge and active low into an active high.
> + * For the inverter to work, the polarity bit in the IRQ_CONFIG register has 
> to
> + * set as per the table below.
> + * (polarity, falling edge, rising edge ) POLARITY
> + * 3'b0 00  Level sensitive active lowLOW
> + * 3'b0 01  Rising edge sensitive NOT USED
> + * 3'b0 10  Falling edge sensitiveLOW
> + * 3'b0 11  Dual Edge sensitive   NOT USED
> + * 3'b1 00  Level sensitive active High   HIGH
> + * 3'b1 01  Falling Edge sensitiveNOT USED
> + * 3'b1 10  Rising edge sensitive HIGH
> + * 3'b1 11  Dual Edge sensitive   HIGH
> + */
> +enum pdc_irq_config_bits {
> + PDC_POLARITY_LOW= 0,
> + PDC_FALLING_EDGE= 2,
> + PDC_POLARITY_HIGH   = 4,
> + PDC_RISING_EDGE = 6,
> + PDC_DUAL_EDGE   = 7,

My previous comment about using binary constants still stands. Please
either address review comments or reply at least. Ignoring reviews is not
an option.

Aside of that I really have to ask about the naming of these constants. Are
these names hardware register nomenclature? If yes, they are disgusting. If
no, they are still disgusting, but should be changed to sensible ones,
which just match the IRQ_TYPE naming convention.

PDC_LEVEL_LOW   = 000b,
PDC_EDGE_FALLING= 010b,



> + switch (type) {
> + case IRQ_TYPE_EDGE_RISING:
> + pdc_type = PDC_RISING_EDGE;
> + type = IRQ_TYPE_EDGE_RISING;

Whats the point of assigning the same value again?

> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + pdc_type = PDC_FALLING_EDGE;
> + type = IRQ_TYPE_EDGE_RISING;
> + break;
> + case IRQ_TYPE_EDGE_BOTH:
> + pdc_type = PDC_DUAL_EDGE;
> + break;
> + case IRQ_TYPE_LEVEL_HIGH:
> + pdc_type = PDC_POLARITY_HIGH;
> + type = IRQ_TYPE_LEVEL_HIGH;

Ditto

Thanks,

tglx

[PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-09 Thread Lina Iyer 
>From : Archana Sathyakumar 

The Power Domain Controller (PDC) on QTI SoCs like SDM845 houses an
interrupt controller along with other domain control functions to handle
interrupt related functions like handle falling edge or active low which
are not detected at the GIC and handle wakeup interrupts.

The interrupt controller is on an always-on domain for the purpose of
waking up the processor. Only a subset of the processor's interrupts are
routed through the PDC to the GIC. The PDC powers on the processors'
domain, when in low power mode and replays pending interrupts so the GIC
may wake up the processor.

Signed-off-by: Archana Sathyakumar 
Signed-off-by: Lina Iyer 
---
 drivers/irqchip/Kconfig|   9 ++
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/qcom-pdc.c | 314 +
 3 files changed, 324 insertions(+)
 create mode 100644 drivers/irqchip/qcom-pdc.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c70476b34a53..506c6aa7f0b4 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -343,4 +343,13 @@ config MESON_IRQ_GPIO
help
  Support Meson SoC Family GPIO Interrupt Multiplexer
 
+config QCOM_PDC
+   bool "QCOM PDC"
+   depends on ARCH_QCOM
+   select IRQ_DOMAIN
+   select IRQ_DOMAIN_HIERARCHY
+   help
+ Power Domain Controller driver to manage and configure wakeup
+ IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
+
 endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d2df34a54d38..280723d83916 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_QCOM_IRQ_COMBINER)   += 
qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)   += irq-uniphier-aidet.o
 obj-$(CONFIG_ARCH_SYNQUACER)   += irq-sni-exiu.o
 obj-$(CONFIG_MESON_IRQ_GPIO)   += irq-meson-gpio.o
+obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
new file mode 100644
index ..714e95858837
--- /dev/null
+++ b/drivers/irqchip/qcom-pdc.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PDC_MAX_IRQS   126
+
+#define CLEAR_INTR(reg, intr)  (reg & ~(1 << intr))
+#define ENABLE_INTR(reg, intr) (reg | (1 << intr))
+
+#define IRQ_ENABLE_BANK0x10
+#define IRQ_i_CFG  0x110
+
+struct pdc_pin_region {
+   u32 pin_base;
+   u32 parent_base;
+   u32 cnt;
+};
+
+static DEFINE_RAW_SPINLOCK(pdc_lock);
+static void __iomem *pdc_base;
+static struct pdc_pin_region *pdc_region;
+static int pdc_region_cnt;
+
+static void pdc_reg_write(int reg, u32 i, u32 val)
+{
+   writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
+}
+
+static u32 pdc_reg_read(int reg, u32 i)
+{
+   return readl_relaxed(pdc_base + reg + i * sizeof(u32));
+}
+
+static void pdc_enable_intr(struct irq_data *d, bool on)
+{
+   int pin_out = d->hwirq;
+   u32 index, mask;
+   u32 enable;
+
+   index = pin_out / 32;
+   mask = pin_out % 32;
+
+   raw_spin_lock(_lock);
+   enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
+   enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
+   pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
+   raw_spin_unlock(_lock);
+}
+
+static void qcom_pdc_gic_mask(struct irq_data *d)
+{
+   pdc_enable_intr(d, false);
+   irq_chip_mask_parent(d);
+}
+
+static void qcom_pdc_gic_unmask(struct irq_data *d)
+{
+   pdc_enable_intr(d, true);
+   irq_chip_unmask_parent(d);
+}
+
+/*
+ * GIC does not handle falling edge or active low. To allow falling edge and
+ * active low interrupts to be handled at GIC, PDC has an inverter that inverts
+ * falling edge into a rising edge and active low into an active high.
+ * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
+ * set as per the table below.
+ * (polarity, falling edge, rising edge ) POLARITY
+ * 3'b0 00  Level sensitive active lowLOW
+ * 3'b0 01  Rising edge sensitive NOT USED
+ * 3'b0 10  Falling edge sensitiveLOW
+ * 3'b0 11  Dual Edge sensitive   NOT USED
+ * 3'b1 00  Level sensitive active High   HIGH
+ * 3'b1 01  Falling Edge sensitiveNOT USED
+ * 3'b1 10  Rising edge sensitive HIGH
+ * 3'b1 11  Dual Edge sensitive   HIGH
+ */
+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,
+};
+
+/**
+ * qcom_pdc_gic_set_type: Configure

[PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs

2018-02-09 Thread Lina Iyer 
>From : Archana Sathyakumar 

The Power Domain Controller (PDC) on QTI SoCs like SDM845 houses an
interrupt controller along with other domain control functions to handle
interrupt related functions like handle falling edge or active low which
are not detected at the GIC and handle wakeup interrupts.

The interrupt controller is on an always-on domain for the purpose of
waking up the processor. Only a subset of the processor's interrupts are
routed through the PDC to the GIC. The PDC powers on the processors'
domain, when in low power mode and replays pending interrupts so the GIC
may wake up the processor.

Signed-off-by: Archana Sathyakumar 
Signed-off-by: Lina Iyer 
---
 drivers/irqchip/Kconfig|   9 ++
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/qcom-pdc.c | 314 +
 3 files changed, 324 insertions(+)
 create mode 100644 drivers/irqchip/qcom-pdc.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c70476b34a53..506c6aa7f0b4 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -343,4 +343,13 @@ config MESON_IRQ_GPIO
help
  Support Meson SoC Family GPIO Interrupt Multiplexer
 
+config QCOM_PDC
+   bool "QCOM PDC"
+   depends on ARCH_QCOM
+   select IRQ_DOMAIN
+   select IRQ_DOMAIN_HIERARCHY
+   help
+ Power Domain Controller driver to manage and configure wakeup
+ IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
+
 endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d2df34a54d38..280723d83916 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_QCOM_IRQ_COMBINER)   += 
qcom-irq-combiner.o
 obj-$(CONFIG_IRQ_UNIPHIER_AIDET)   += irq-uniphier-aidet.o
 obj-$(CONFIG_ARCH_SYNQUACER)   += irq-sni-exiu.o
 obj-$(CONFIG_MESON_IRQ_GPIO)   += irq-meson-gpio.o
+obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
new file mode 100644
index ..714e95858837
--- /dev/null
+++ b/drivers/irqchip/qcom-pdc.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PDC_MAX_IRQS   126
+
+#define CLEAR_INTR(reg, intr)  (reg & ~(1 << intr))
+#define ENABLE_INTR(reg, intr) (reg | (1 << intr))
+
+#define IRQ_ENABLE_BANK0x10
+#define IRQ_i_CFG  0x110
+
+struct pdc_pin_region {
+   u32 pin_base;
+   u32 parent_base;
+   u32 cnt;
+};
+
+static DEFINE_RAW_SPINLOCK(pdc_lock);
+static void __iomem *pdc_base;
+static struct pdc_pin_region *pdc_region;
+static int pdc_region_cnt;
+
+static void pdc_reg_write(int reg, u32 i, u32 val)
+{
+   writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
+}
+
+static u32 pdc_reg_read(int reg, u32 i)
+{
+   return readl_relaxed(pdc_base + reg + i * sizeof(u32));
+}
+
+static void pdc_enable_intr(struct irq_data *d, bool on)
+{
+   int pin_out = d->hwirq;
+   u32 index, mask;
+   u32 enable;
+
+   index = pin_out / 32;
+   mask = pin_out % 32;
+
+   raw_spin_lock(_lock);
+   enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
+   enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
+   pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
+   raw_spin_unlock(_lock);
+}
+
+static void qcom_pdc_gic_mask(struct irq_data *d)
+{
+   pdc_enable_intr(d, false);
+   irq_chip_mask_parent(d);
+}
+
+static void qcom_pdc_gic_unmask(struct irq_data *d)
+{
+   pdc_enable_intr(d, true);
+   irq_chip_unmask_parent(d);
+}
+
+/*
+ * GIC does not handle falling edge or active low. To allow falling edge and
+ * active low interrupts to be handled at GIC, PDC has an inverter that inverts
+ * falling edge into a rising edge and active low into an active high.
+ * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
+ * set as per the table below.
+ * (polarity, falling edge, rising edge ) POLARITY
+ * 3'b0 00  Level sensitive active lowLOW
+ * 3'b0 01  Rising edge sensitive NOT USED
+ * 3'b0 10  Falling edge sensitiveLOW
+ * 3'b0 11  Dual Edge sensitive   NOT USED
+ * 3'b1 00  Level sensitive active High   HIGH
+ * 3'b1 01  Falling Edge sensitiveNOT USED
+ * 3'b1 10  Rising edge sensitive HIGH
+ * 3'b1 11  Dual Edge sensitive   HIGH
+ */
+enum pdc_irq_config_bits {
+   PDC_POLARITY_LOW= 0,
+   PDC_FALLING_EDGE= 2,
+   PDC_POLARITY_HIGH   = 4,
+   PDC_RISING_EDGE = 6,
+   PDC_DUAL_EDGE   = 7,
+};
+
+/**
+ * qcom_pdc_gic_set_type: Configure PDC for the interrupt
+ *
+ * @d: the interrupt data
+ * @type: the