Add documentation for the marvell,ecc-enable properties which can be
used to enable ECC on the Marvell aurora cache.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Notes:
Changes in v7:
- remove marvell,ecc-disable
Changes in v6:
- new (split binding doc from implementation).
Documentation/devicetree/bindings/arm/l2c2x0.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
index bfc5c185561c..913a8cd8b2c0 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
@@ -176,6 +176,10 @@ properties:
description: disable parity checking on the L2 cache (L220 or PL310).
type: boolean
+ marvell,ecc-enable:
+ description: enable ECC protection on the L2 cache
+ type: boolean
+
arm,outer-sync-disable:
description: disable the outer sync operation on the L2 cache.
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
--
2.22.0
