Let's add an hypothetical "caching mode" smmuv3 model (not yet
discussed for IORT spec) and enable the TLBI_ON_MAP option for
this latter.
Signed-off-by: Eric Auger <eric.au...@redhat.com>
---
drivers/iommu/arm-smmu-v3.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 690247b..a1c10af 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -422,6 +422,10 @@
#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2
#endif
+#ifndef ACPI_IORT_SMMU_V3_CACHING_MODE
+#define ACPI_IORT_SMMU_V3_CACHING_MODE 0x3
+#endif
+
static bool disable_bypass;
module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
@@ -2673,6 +2677,9 @@ static void acpi_smmu_get_options(u32 model, struct
arm_smmu_device *smmu)
case ACPI_IORT_SMMU_HISILICON_HI161X:
smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH;
break;
+ case ACPI_IORT_SMMU_V3_CACHING_MODE:
+ smmu->options |= ARM_SMMU_OPT_TLBI_ON_MAP;
+ break;
}
dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options);
--
2.5.5
