On Thu, Sep 14, 2017 at 04:17:36PM +0900, Masahiro Yamada wrote:
> This example allocates too much for register regions. Especially,
> there are only two registers in the "nand_data" interface of this
> hardware (ADDR: 0x00, DATA: 0x10).
>
> Signed-off-by: Masahiro Yamada
On Thu, Sep 14, 2017 at 04:17:36PM +0900, Masahiro Yamada wrote:
> This example allocates too much for register regions. Especially,
> there are only two registers in the "nand_data" interface of this
> hardware (ADDR: 0x00, DATA: 0x10).
>
> Signed-off-by: Masahiro Yamada
> ---
>
>
2017-09-21 15:09 GMT+09:00 Oleksij Rempel :
> Hi,
>
> On 21.09.2017 07:26, Masahiro Yamada wrote:
>>
>> Hi.
>
>
> ..
>
>>> Hm.. according to
>>>
>>> https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
>>> Table 13-18: NAND Controller Module Data
2017-09-21 15:09 GMT+09:00 Oleksij Rempel :
> Hi,
>
> On 21.09.2017 07:26, Masahiro Yamada wrote:
>>
>> Hi.
>
>
> ..
>
>>> Hm.. according to
>>>
>>> https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
>>> Table 13-18: NAND Controller Module Data Space Address Range
Hi,
On 21.09.2017 07:26, Masahiro Yamada wrote:
Hi.
..
Hm.. according to
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
Table 13-18: NAND Controller Module Data Space Address Range
Module Instance Start AddressEnd Address
NAND_DATA
Hi,
On 21.09.2017 07:26, Masahiro Yamada wrote:
Hi.
..
Hm.. according to
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
Table 13-18: NAND Controller Module Data Space Address Range
Module Instance Start AddressEnd Address
NAND_DATA
Hi.
2017-09-14 18:06 GMT+09:00 Oleksij Rempel :
> On 14.09.2017 10:16, Masahiro Yamada wrote:
>>
>> Hi.
>>
>>
>> 2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
>>>
>>> Hi,
>>>
>>> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
>>
Hi.
2017-09-14 18:06 GMT+09:00 Oleksij Rempel :
> On 14.09.2017 10:16, Masahiro Yamada wrote:
>>
>> Hi.
>>
>>
>> 2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
>>>
>>> Hi,
>>>
>>> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
>>
>>
>> I think so.
>> (also
On 14.09.2017 10:16, Masahiro Yamada wrote:
Hi.
2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
Hi,
i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
Hm.. according to
On 14.09.2017 10:16, Masahiro Yamada wrote:
Hi.
2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
Hi,
i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
Hm.. according to
Hi.
2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
> Hi,
>
> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
The wrong property "dma-mask" was removed by
commit
Hi.
2017-09-14 17:04 GMT+09:00 Oleksij Rempel :
> Hi,
>
> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
The wrong property "dma-mask" was removed by
commit
Hi,
i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
On 14.09.2017 09:17, Masahiro Yamada wrote:
This example allocates too much for register regions. Especially,
there are only two registers in the "nand_data" interface of this
hardware (ADDR: 0x00, DATA: 0x10).
Hi,
i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
On 14.09.2017 09:17, Masahiro Yamada wrote:
This example allocates too much for register regions. Especially,
there are only two registers in the "nand_data" interface of this
hardware (ADDR: 0x00, DATA: 0x10).
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