Re: [PATCH 01/10] dt-bindings: pinctrl: Add bindings for Actions S900 SoC
On Sun, Feb 18, 2018 at 02:14:24AM +0530, Manivannan Sadhasivam wrote: > Add pinctrl bindings for Actions Semi S900 SoC > > Signed-off-by: Manivannan Sadhasivam > --- > .../bindings/pinctrl/actions,s900-pinctrl.txt | 171 > + > 1 file changed, 171 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt Reviewed-by: Rob Herring
Re: [PATCH 01/10] dt-bindings: pinctrl: Add bindings for Actions S900 SoC
Hi Andreas, On Sat, Feb 17, 2018 at 10:03:53PM +0100, Andreas Färber wrote: > Am 17.02.2018 um 21:44 schrieb Manivannan Sadhasivam: > > Add pinctrl bindings for Actions Semi S900 SoC > > > > Signed-off-by: Manivannan Sadhasivam > > --- > > .../bindings/pinctrl/actions,s900-pinctrl.txt | 171 > > + > > 1 file changed, 171 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > > > > diff --git > > a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > > b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > > new file mode 100644 > > index ..ee7d3ecd9bd9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > > @@ -0,0 +1,171 @@ > > +Actions Semi S900 Pin Controller > > So you are targeting to have one bindings file per SoC? > Yes. Similar to what Qcom drivers are doing! Having a single binding will look messy if we add support for other OWL family SoC's like S500, S700... > > + > > +This binding describes the pin controller found in the S900 SoC. > > + > > +Required Properties: > > + > > +- compatible: Should be "actions,s900-pinctrl" > > +- reg: Should contain the register base address and size of > > +the pin controller. > > +- clocks: phandle of the clock feeding the pin controller > > + > > +Please refer to pinctrl-bindings.txt in this directory for details of the > > +common pinctrl bindings used by client devices, including the meaning of > > the > > +phrase "pin configuration node". > > + > > +The pin configuration nodes act as a container for an arbitrary number of > > +subnodes. Each of these subnodes represents some desired configuration for > > a > > +pin, a group, or a list of pins or groups. This configuration can include > > the > > +mux function to select on those group(s), and various pin configuration > > +parameters, such as pull-up, drive strength, etc. > > + > > +PIN CONFIGURATION NODES: > > + > > +The name of each subnode is not important; all subnodes should be > > enumerated > > +and processed purely based on their content. > > + > > +Each subnode only affects those parameters that are explicitly listed. In > > +other words, a subnode that lists a mux function but no pin configuration > > +parameters implies no information about any pin configuration parameters. > > +Similarly, a pin subnode that describes a pullup parameter implies no > > +information about e.g. the mux function. > > + > > +Pinmux functions are available only for the pin groups while pinconf > > +parameters are available for both pin groups and individual pins. > > + > > +The following generic properties as defined in pinctrl-bindings.txt are > > valid > > +to specify in a pin configuration subnode: > > + > > +Required Properties: > > + > > +- pins: An array of strings, each string containing the name of > > a pin. > > + These pins are used for selecting the pull control and > > schmitt > > + trigger parameters. The following are the list of pins > > + available: > > + > > + ETH_TXD0, ETH_TXD1, ETH_TXEN, ETH_RXER, ETH_CRS_DV, > > + ETH_RXD1, ETH_RXD0, ETH_REF_CLK, ETH_MDC, ETH_MDIO, > > + SIRQ0, SIRQ1, SIRQ2, I2S_D0, I2S_BCLK0, I2S_LRCLK0, > > + I2S_MCLK0, I2S_D1, I2S_BCLK1, I2S_LRCLK1, I2S_MCLK1, > > + PCM1_IN, PCM1_CLK, PCM1_SYNC, PCM1_OUT, ERAM_A5, > > + ERAM_A6, ERAM_A7, ERAM_A8, ERAM_A9, ERAM_A10, ERAM_A11, > > + LVDS_OEP, LVDS_OEN, LVDS_ODP, LVDS_ODN, LVDS_OCP, > > + LVDS_OCN, LVDS_OBP, LVDS_OBN, LVDS_OAP, LVDS_OAN, > > + LVDS_EEP, LVDS_EEN, LVDS_EDP, LVDS_EDN, LVDS_ECP, > > + LVDS_ECN, LVDS_EBP, LVDS_EBN, LVDS_EAP, LVDS_EAN, > > + SD0_D0, SD0_D1, SD0_D2, SD0_D3, SD1_D0, SD1_D1, > > + SD1_D2, SD1_D3, SD0_CMD, SD0_CLK, SD1_CMD, SD1_CLK, > > + SPI0_SCLK, SPI0_SS, SPI0_MISO, SPI0_MOSI, UART0_RX, > > + UART0_TX, UART2_RX, UART2_TX, UART2_RTSB, UART2_CTSB, > > + UART3_RX, UART3_TX, UART3_RTSB, UART3_CTSB, UART4_RX, > > + UART4_TX, I2C0_SCLK, I2C0_SDATA, I2C1_SCLK, I2C1_SDATA, > > + I2C2_SCLK, I2C2_SDATA, CSI0_DN0, CSI0_DP0, CSI0_DN1, > > + CSI0_DP1, CSI0_CN, CSI0_CP, CSI0_DN2, CSI0_DP2, CSI0_DN3, > > + CSI0_DP3, DSI_DP3, DSI_DN3, DSI_DP1, DSI_DN1, DSI_CP, > > + DSI_CN, DSI_DP0, DSI_DN0, DSI_DP2, DSI_DN2, SENSOR0_PCLK, > > + CSI1_DN0,CSI1_DP0,CSI1_DN1, CSI1_DP1, CSI1_CN, CSI1_CP, > > + SENSOR0_CKOUT, NAND0_D0, NAND0_D1, NAND0_D2, NAND0_D3, > > + NAND0_D4, NAND0_D5, NAND0_D6, NAND0_D7, NAND0_DQS, > > + NAND0_DQSN, NAND0_ALE, NAND0_CLE, NAND0_CEB0
Re: [PATCH 01/10] dt-bindings: pinctrl: Add bindings for Actions S900 SoC
Am 17.02.2018 um 21:44 schrieb Manivannan Sadhasivam: > Add pinctrl bindings for Actions Semi S900 SoC > > Signed-off-by: Manivannan Sadhasivam > --- > .../bindings/pinctrl/actions,s900-pinctrl.txt | 171 > + > 1 file changed, 171 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > > diff --git > a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > new file mode 100644 > index ..ee7d3ecd9bd9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt > @@ -0,0 +1,171 @@ > +Actions Semi S900 Pin Controller So you are targeting to have one bindings file per SoC? > + > +This binding describes the pin controller found in the S900 SoC. > + > +Required Properties: > + > +- compatible: Should be "actions,s900-pinctrl" > +- reg: Should contain the register base address and size of > +the pin controller. > +- clocks: phandle of the clock feeding the pin controller > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices, including the meaning of the > +phrase "pin configuration node". > + > +The pin configuration nodes act as a container for an arbitrary number of > +subnodes. Each of these subnodes represents some desired configuration for a > +pin, a group, or a list of pins or groups. This configuration can include the > +mux function to select on those group(s), and various pin configuration > +parameters, such as pull-up, drive strength, etc. > + > +PIN CONFIGURATION NODES: > + > +The name of each subnode is not important; all subnodes should be enumerated > +and processed purely based on their content. > + > +Each subnode only affects those parameters that are explicitly listed. In > +other words, a subnode that lists a mux function but no pin configuration > +parameters implies no information about any pin configuration parameters. > +Similarly, a pin subnode that describes a pullup parameter implies no > +information about e.g. the mux function. > + > +Pinmux functions are available only for the pin groups while pinconf > +parameters are available for both pin groups and individual pins. > + > +The following generic properties as defined in pinctrl-bindings.txt are valid > +to specify in a pin configuration subnode: > + > +Required Properties: > + > +- pins: An array of strings, each string containing the name of a > pin. > + These pins are used for selecting the pull control and > schmitt > + trigger parameters. The following are the list of pins > + available: > + > + ETH_TXD0, ETH_TXD1, ETH_TXEN, ETH_RXER, ETH_CRS_DV, > + ETH_RXD1, ETH_RXD0, ETH_REF_CLK, ETH_MDC, ETH_MDIO, > + SIRQ0, SIRQ1, SIRQ2, I2S_D0, I2S_BCLK0, I2S_LRCLK0, > + I2S_MCLK0, I2S_D1, I2S_BCLK1, I2S_LRCLK1, I2S_MCLK1, > + PCM1_IN, PCM1_CLK, PCM1_SYNC, PCM1_OUT, ERAM_A5, > + ERAM_A6, ERAM_A7, ERAM_A8, ERAM_A9, ERAM_A10, ERAM_A11, > + LVDS_OEP, LVDS_OEN, LVDS_ODP, LVDS_ODN, LVDS_OCP, > + LVDS_OCN, LVDS_OBP, LVDS_OBN, LVDS_OAP, LVDS_OAN, > + LVDS_EEP, LVDS_EEN, LVDS_EDP, LVDS_EDN, LVDS_ECP, > + LVDS_ECN, LVDS_EBP, LVDS_EBN, LVDS_EAP, LVDS_EAN, > + SD0_D0, SD0_D1, SD0_D2, SD0_D3, SD1_D0, SD1_D1, > + SD1_D2, SD1_D3, SD0_CMD, SD0_CLK, SD1_CMD, SD1_CLK, > + SPI0_SCLK, SPI0_SS, SPI0_MISO, SPI0_MOSI, UART0_RX, > + UART0_TX, UART2_RX, UART2_TX, UART2_RTSB, UART2_CTSB, > + UART3_RX, UART3_TX, UART3_RTSB, UART3_CTSB, UART4_RX, > + UART4_TX, I2C0_SCLK, I2C0_SDATA, I2C1_SCLK, I2C1_SDATA, > + I2C2_SCLK, I2C2_SDATA, CSI0_DN0, CSI0_DP0, CSI0_DN1, > + CSI0_DP1, CSI0_CN, CSI0_CP, CSI0_DN2, CSI0_DP2, CSI0_DN3, > + CSI0_DP3, DSI_DP3, DSI_DN3, DSI_DP1, DSI_DN1, DSI_CP, > + DSI_CN, DSI_DP0, DSI_DN0, DSI_DP2, DSI_DN2, SENSOR0_PCLK, > + CSI1_DN0,CSI1_DP0,CSI1_DN1, CSI1_DP1, CSI1_CN, CSI1_CP, > + SENSOR0_CKOUT, NAND0_D0, NAND0_D1, NAND0_D2, NAND0_D3, > + NAND0_D4, NAND0_D5, NAND0_D6, NAND0_D7, NAND0_DQS, > + NAND0_DQSN, NAND0_ALE, NAND0_CLE, NAND0_CEB0, NAND0_CEB1, > + NAND0_CEB2, NAND0_CEB3, NAND1_D0, NAND1_D1, NAND1_D2, > + NAND1_D3, NAND1_D4, NAND1_D5, NAND1_D6, NAND1_D7, > NAND1_DQS, > + NAND1_DQSN, NAND1_ALE, NAND1_CLE, NAND1_CEB0, NAND1_CEB1, > + NAND1_CEB2, NAND1_CEB3, SGPIO0, SGPIO1, SGPIO2, SGPIO3 Should be lower-case? > + > +- groups: An array of strings, each string containing the name of a
