Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread Mark Rutland
On Fri, Apr 06, 2018 at 06:22:11PM +0100, Mark Rutland wrote: > Digging a bit, I also thing that our ct_user_exit and ct_user_enter > usage is on dodgy ground today. > > For example, in el0_dbg we call do_debug_exception() *before* calling > ct_user_exit. Which I believe means we'd use RCU while s

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread Mark Rutland
On Fri, Apr 06, 2018 at 06:30:50PM +0100, James Morse wrote: > Hi Mark, > > On 06/04/18 18:22, Mark Rutland wrote: > > Digging a bit, I also thing that our ct_user_exit and ct_user_enter > > usage is on dodgy ground today. > > [...] > > > I think similar applies to SDEI; we don't negotiate with

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread James Morse
Hi Mark, On 06/04/18 18:22, Mark Rutland wrote: > Digging a bit, I also thing that our ct_user_exit and ct_user_enter > usage is on dodgy ground today. [...] > I think similar applies to SDEI; we don't negotiate with RCU prior to > invoking handlers, which might need RCU. The arch code's __sdei

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread Mark Rutland
On Fri, Apr 06, 2018 at 07:54:02PM +0300, Yury Norov wrote: > In general, kick_all_cpus_sync() is needed to switch contexts. But exit from > userspace is anyway the switch of context. And while in userspace, we cannot > do something wrong on kernel side. For me it means that we can safely drop > IP

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread Yury Norov
On Fri, Apr 06, 2018 at 11:02:56AM +0100, James Morse wrote: > Hi Yury, > > An ISB at the beginning of the vectors? This is odd, taking an IRQ to get in > here would be a context-synchronization-event too, so the ISB is superfluous. > > The ARM-ARM has a list of 'Context-Synchronization event's

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread Mark Rutland
On Thu, Apr 05, 2018 at 08:17:56PM +0300, Yury Norov wrote: > Kernel text patching framework relies on IPI to ensure that other > SMP cores observe the change. Target core calls isb() in IPI handler > path, but not at the beginning of el1_irq entry. There's a chance > that modified instruction will

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread James Morse
Hi Yury, On 05/04/18 18:17, Yury Norov wrote: > Kernel text patching framework relies on IPI to ensure that other > SMP cores observe the change. Target core calls isb() in IPI handler (Odd, if its just to synchronize the CPU, taking the IPI should be enough). > path, but not at the beginning o