Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Shivappa Vikas
On Wed, 4 Apr 2018, Thomas Gleixner wrote: > On Tue, 3 Apr 2018, Shivappa Vikas wrote: > > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > > > The L2 external bandwidth is higher than the L3 external bandwidth. > > > > > > Is there any information

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Shivappa Vikas
On Wed, 4 Apr 2018, Thomas Gleixner wrote: > On Tue, 3 Apr 2018, Shivappa Vikas wrote: > > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > > > The L2 external bandwidth is higher than the L3 external bandwidth. > > > > > > Is there any information

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Shivappa Vikas wrote: > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > The proposed new interface has no upper limit. The existing percentage > > based implementation has at least some notion of limit and scale; not > > really helpful either because of the hardware

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Shivappa Vikas wrote: > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > The proposed new interface has no upper limit. The existing percentage > > based implementation has at least some notion of limit and scale; not > > really helpful either because of the hardware

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Shivappa Vikas wrote: > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > > The L2 external bandwidth is higher than the L3 external bandwidth. > > > > Is there any information available from CPUID or whatever source which > > allows

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-04 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Shivappa Vikas wrote: > On Tue, 3 Apr 2018, Thomas Gleixner wrote: > > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > > The L2 external bandwidth is higher than the L3 external bandwidth. > > > > Is there any information available from CPUID or whatever source which > > allows

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Shivappa Vikas
On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Thu, 29 Mar 2018, Vikas Shivappa wrote: You said above: This may lead to confusion in scenarios below: Reading the blurb after that creates even more confusion than being helpful. First of all this

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Shivappa Vikas
On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Thu, 29 Mar 2018, Vikas Shivappa wrote: You said above: This may lead to confusion in scenarios below: Reading the blurb after that creates even more confusion than being helpful. First of all this

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Shivappa Vikas
On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Thu, 29 Mar 2018, Vikas Shivappa wrote: +Memory bandwidth(b/w) in MegaBytes +-- + +Memory bandwidth is a core specific mechanism which means that when the +Memory b/w percentage is specified in the schemata per

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Shivappa Vikas
On Tue, 3 Apr 2018, Thomas Gleixner wrote: On Thu, 29 Mar 2018, Vikas Shivappa wrote: +Memory bandwidth(b/w) in MegaBytes +-- + +Memory bandwidth is a core specific mechanism which means that when the +Memory b/w percentage is specified in the schemata per

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Thomas Gleixner wrote: > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > You said above: > > > This may lead to confusion in scenarios below: > > Reading the blurb after that creates even more confusion than being > helpful. > > First of all this information should not be under

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Thomas Gleixner
On Tue, 3 Apr 2018, Thomas Gleixner wrote: > On Thu, 29 Mar 2018, Vikas Shivappa wrote: > You said above: > > > This may lead to confusion in scenarios below: > > Reading the blurb after that creates even more confusion than being > helpful. > > First of all this information should not be under

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Thomas Gleixner
On Thu, 29 Mar 2018, Vikas Shivappa wrote: > +Memory bandwidth(b/w) in MegaBytes > +-- > + > +Memory bandwidth is a core specific mechanism which means that when the > +Memory b/w percentage is specified in the schemata per package it > +actually is applied on a per

Re: [PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

2018-04-03 Thread Thomas Gleixner
On Thu, 29 Mar 2018, Vikas Shivappa wrote: > +Memory bandwidth(b/w) in MegaBytes > +-- > + > +Memory bandwidth is a core specific mechanism which means that when the > +Memory b/w percentage is specified in the schemata per package it > +actually is applied on a per