On Wed, 4 Apr 2018, Thomas Gleixner wrote:
> On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> > On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > > On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> > > The L2 external bandwidth is higher than the L3 external bandwidth.
> > >
> > > Is there any information
On Wed, 4 Apr 2018, Thomas Gleixner wrote:
> On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> > On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > > On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> > > The L2 external bandwidth is higher than the L3 external bandwidth.
> > >
> > > Is there any information
On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > The proposed new interface has no upper limit. The existing percentage
> > based implementation has at least some notion of limit and scale; not
> > really helpful either because of the hardware
On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > The proposed new interface has no upper limit. The existing percentage
> > based implementation has at least some notion of limit and scale; not
> > really helpful either because of the hardware
On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> > The L2 external bandwidth is higher than the L3 external bandwidth.
> >
> > Is there any information available from CPUID or whatever source which
> > allows
On Tue, 3 Apr 2018, Shivappa Vikas wrote:
> On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> > On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> > The L2 external bandwidth is higher than the L3 external bandwidth.
> >
> > Is there any information available from CPUID or whatever source which
> > allows
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
You said above:
This may lead to confusion in scenarios below:
Reading the blurb after that creates even more confusion than being
helpful.
First of all this
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
You said above:
This may lead to confusion in scenarios below:
Reading the blurb after that creates even more confusion than being
helpful.
First of all this
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
+Memory bandwidth(b/w) in MegaBytes
+--
+
+Memory bandwidth is a core specific mechanism which means that when the
+Memory b/w percentage is specified in the schemata per
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
+Memory bandwidth(b/w) in MegaBytes
+--
+
+Memory bandwidth is a core specific mechanism which means that when the
+Memory b/w percentage is specified in the schemata per
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> You said above:
>
> > This may lead to confusion in scenarios below:
>
> Reading the blurb after that creates even more confusion than being
> helpful.
>
> First of all this information should not be under
On Tue, 3 Apr 2018, Thomas Gleixner wrote:
> On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> You said above:
>
> > This may lead to confusion in scenarios below:
>
> Reading the blurb after that creates even more confusion than being
> helpful.
>
> First of all this information should not be under
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> +Memory bandwidth(b/w) in MegaBytes
> +--
> +
> +Memory bandwidth is a core specific mechanism which means that when the
> +Memory b/w percentage is specified in the schemata per package it
> +actually is applied on a per
On Thu, 29 Mar 2018, Vikas Shivappa wrote:
> +Memory bandwidth(b/w) in MegaBytes
> +--
> +
> +Memory bandwidth is a core specific mechanism which means that when the
> +Memory b/w percentage is specified in the schemata per package it
> +actually is applied on a per
14 matches
Mail list logo