On Mon, Jan 19, 2015 at 01:54:26PM +, Arnd Bergmann wrote:
> On Monday 19 January 2015 13:38:53 Gabriel Fernandez wrote:
> >
> > On 18 December 2014 at 05:58, Jingoo Han wrote:
> >
> > > On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
> > > > On Wednesday 17 December 2014
On Monday 19 January 2015 13:38:53 Gabriel Fernandez wrote:
>
> On 18 December 2014 at 05:58, Jingoo Han wrote:
>
> > On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
> > > On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> > > > ST sti SoCs PCIe IPs are built around
Hi Arnd, Jingoo,
On 18 December 2014 at 05:58, Jingoo Han wrote:
> On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
>> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
>> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
>> > But in these SoCs PCIe IP doesn't
Hi Arnd, Jingoo,
On 18 December 2014 at 05:58, Jingoo Han jg1@samsung.com wrote:
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe
On Monday 19 January 2015 13:38:53 Gabriel Fernandez wrote:
On 18 December 2014 at 05:58, Jingoo Han jg1@samsung.com wrote:
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
ST sti SoCs PCIe IPs are built
On Mon, Jan 19, 2015 at 01:54:26PM +, Arnd Bergmann wrote:
On Monday 19 January 2015 13:38:53 Gabriel Fernandez wrote:
On 18 December 2014 at 05:58, Jingoo Han jg1@samsung.com wrote:
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
On Wednesday 17 December 2014
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> > But in these SoCs PCIe IP doesn't support IO.
Hi Gabriel,
I cannot understand how ST sti SoCs PCIe IP
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> But in these SoCs PCIe IP doesn't support IO.
>
> To support this, add setup_bus() to pcie_host_ops.
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Gabriel
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
To support this, add setup_bus() to pcie_host_ops.
Signed-off-by: Fabrice Gasnier fabrice.gasn...@st.com
Signed-off-by:
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
ST sti SoCs PCIe IPs are built around DesignWare IP Core.
But in these SoCs PCIe IP doesn't support IO.
Hi Gabriel,
I cannot understand how ST sti SoCs PCIe IP does
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