在 2016/9/24 9:45, Jiancheng Xue 写道:
> 在 2016/9/24 1:47, Rob Herring 写道:
>> On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
>>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
>>> Generator) module generates clock and reset signals used
>>> by other module blocks on SoC.
在 2016/9/24 9:45, Jiancheng Xue 写道:
> 在 2016/9/24 1:47, Rob Herring 写道:
>> On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
>>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
>>> Generator) module generates clock and reset signals used
>>> by other module blocks on SoC.
在 2016/9/24 1:47, Rob Herring 写道:
> On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
>> Generator) module generates clock and reset signals used
>> by other module blocks on SoC.
>>
>> Signed-off-by: Jiancheng Xue
在 2016/9/24 1:47, Rob Herring 写道:
> On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
>> Generator) module generates clock and reset signals used
>> by other module blocks on SoC.
>>
>> Signed-off-by: Jiancheng Xue
>> ---
>>
On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Jiancheng Xue
> ---
> change log
>
On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote:
> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Jiancheng Xue
> ---
> change log
> v2:
> - Fixed compiling error
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