Quoting Eddie James (2018-03-08 12:57:19)
> Some of the Aspeed clocks are disabled by setting the relevant bit in
> the "clock stop control" register to one, while others are disabled by
> setting their bit to zero. The driver already uses a flag per gate to
> identify this behavior, but doesn't a
On Fri, Mar 9, 2018 at 7:27 AM, Eddie James wrote:
> Some of the Aspeed clocks are disabled by setting the relevant bit in
> the "clock stop control" register to one, while others are disabled by
> setting their bit to zero. The driver already uses a flag per gate to
> identify this behavior, but
2 matches
Mail list logo
