Re: [PATCH v2 3/5] arm64: dts: rockchip: add tsadc node for rk3328 SoC
Am Freitag, 4. August 2017, 16:06:14 CEST schrieb Rocky Hao: > add tsadc needed main information for rk3328 SoC. > 5Hz is the max clock rate supported by tsadc module. > > Signed-off-by: Rocky Hao applied for 4.14 with some property reordering Thanks Heiko
Re: [PATCH v2 3/5] arm64: dts: rockchip: add tsadc node for rk3328 SoC
Am Freitag, 11. August 2017, 17:45:00 CEST schrieb rocky.hao:
>
> 在 2017/8/11 14:38, Caesar Wang 写道:
> > 在 2017年08月04日 16:06, Rocky Hao 写道:
> >> add tsadc needed main information for rk3328 SoC.
> >> 5Hz is the max clock rate supported by tsadc module.
> >>
> >> Signed-off-by: Rocky Hao
> >> ---
> >> Change in v2:
> >> - remove gerrit Change-Id
> >>
> >> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20
> >> 1 file changed, 20 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> >> b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> >> index db4b2708084d..186fb93fdffd 100644
> >> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> >> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> >> @@ -308,6 +308,26 @@
> >> interrupts = ;
> >> };
> >> +tsadc: tsadc@ff25 {
> >> +compatible = "rockchip,rk3328-tsadc";
> >> +reg = <0x0 0xff25 0x0 0x100>;
> >> +interrupts = ;
> >> +rockchip,grf = <&grf>;
> >> +clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
> >> +clock-names = "tsadc", "apb_pclk";
> >> +assigned-clocks = <&cru SCLK_TSADC>;
> >> +assigned-clock-rates = <5>;
> >> +resets = <&cru SRST_TSADC>;
> >> +reset-names = "tsadc-apb";
> >> +pinctrl-names = "init", "default", "sleep";
> >> +pinctrl-0 = <&otp_gpio>;
> >> +pinctrl-1 = <&otp_out>;
> >> +pinctrl-2 = <&otp_gpio>;
> >> +#thermal-sensor-cells = <1>;
> >
> > Only one sensor, so maybe the value should be 0.
> Caesar, #thermal-sensor-cells means parameter counts used to match the
> proper sensor registered. Both 0 and 1 work well.
>
> Case 0, i.e. #thermal-sensor-cells = <0>, it uses the default channel
> number 0 to match tsadc channal.
> Case 1, i.e. #thermal-sensor-cells = <1>, it uses the setting
> "thermal-sensors = <&tsadc 0>;" to match tsadc channal.
>
> Case 1 provides more readable info than case 0. By my understanding,
> using the default value such as case 0, is not a good coding style.
Also, the binding for the tsadc controller specifies
#thermal-sensor-cells: 1
And the IP block in general can of course handle multiple channels,
so it should also stay that way in the dts.
Heiko
> >
> >> +rockchip,hw-tshut-temp = <10>;
> >> +status = "disabled";
> >> +};
> >> +
> >> saradc: adc@ff28 {
> >> compatible = "rockchip,rk3328-saradc",
> >> "rockchip,rk3399-saradc";
> >> reg = <0x0 0xff28 0x0 0x100>;
> >
> >
> >
> >
>
>
>
Re: [PATCH v2 3/5] arm64: dts: rockchip: add tsadc node for rk3328 SoC
在 2017/8/11 14:38, Caesar Wang 写道:
在 2017年08月04日 16:06, Rocky Hao 写道:
add tsadc needed main information for rk3328 SoC.
5Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index db4b2708084d..186fb93fdffd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -308,6 +308,26 @@
interrupts = ;
};
+tsadc: tsadc@ff25 {
+compatible = "rockchip,rk3328-tsadc";
+reg = <0x0 0xff25 0x0 0x100>;
+interrupts = ;
+rockchip,grf = <&grf>;
+clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+clock-names = "tsadc", "apb_pclk";
+assigned-clocks = <&cru SCLK_TSADC>;
+assigned-clock-rates = <5>;
+resets = <&cru SRST_TSADC>;
+reset-names = "tsadc-apb";
+pinctrl-names = "init", "default", "sleep";
+pinctrl-0 = <&otp_gpio>;
+pinctrl-1 = <&otp_out>;
+pinctrl-2 = <&otp_gpio>;
+#thermal-sensor-cells = <1>;
Only one sensor, so maybe the value should be 0.
Caesar, #thermal-sensor-cells means parameter counts used to match the
proper sensor registered. Both 0 and 1 work well.
Case 0, i.e. #thermal-sensor-cells = <0>, it uses the default channel
number 0 to match tsadc channal.
Case 1, i.e. #thermal-sensor-cells = <1>, it uses the setting
"thermal-sensors = <&tsadc 0>;" to match tsadc channal.
Case 1 provides more readable info than case 0. By my understanding,
using the default value such as case 0, is not a good coding style.
+rockchip,hw-tshut-temp = <10>;
+status = "disabled";
+};
+
saradc: adc@ff28 {
compatible = "rockchip,rk3328-saradc",
"rockchip,rk3399-saradc";
reg = <0x0 0xff28 0x0 0x100>;
Re: [PATCH v2 3/5] arm64: dts: rockchip: add tsadc node for rk3328 SoC
在 2017年08月04日 16:06, Rocky Hao 写道:
add tsadc needed main information for rk3328 SoC.
5Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index db4b2708084d..186fb93fdffd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -308,6 +308,26 @@
interrupts = ;
};
+ tsadc: tsadc@ff25 {
+ compatible = "rockchip,rk3328-tsadc";
+ reg = <0x0 0xff25 0x0 0x100>;
+ interrupts = ;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ assigned-clocks = <&cru SCLK_TSADC>;
+ assigned-clock-rates = <5>;
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ #thermal-sensor-cells = <1>;
Only one sensor, so maybe the value should be 0.
+ rockchip,hw-tshut-temp = <10>;
+ status = "disabled";
+ };
+
saradc: adc@ff28 {
compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff28 0x0 0x100>;
