Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-27 Thread Thierry Reding
On Sat, Mar 03, 2018 at 06:34:50AM +0800, Sean Wang wrote: > On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote: > > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > > > From: Sean Wang > > > > > > Since the offset for both registers,

Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-27 Thread Thierry Reding
On Sat, Mar 03, 2018 at 06:34:50AM +0800, Sean Wang wrote: > On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote: > > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > > > From: Sean Wang > > > > > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to

Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-02 Thread Sean Wang
On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote: > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > > From: Sean Wang > > > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to > > control PWM4 or PWM5 are distinct from

Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-02 Thread Sean Wang
On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote: > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > > From: Sean Wang > > > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to > > control PWM4 or PWM5 are distinct from the other PWMs, whose

Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-02 Thread Thierry Reding
On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > From: Sean Wang > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to > control PWM4 or PWM5 are distinct from the other PWMs, whose wrong > programming on PWM hardware causes

Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623

2018-03-02 Thread Thierry Reding
On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote: > From: Sean Wang > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to > control PWM4 or PWM5 are distinct from the other PWMs, whose wrong > programming on PWM hardware causes waveform cannot be output