On Sat, Mar 03, 2018 at 06:34:50AM +0800, Sean Wang wrote:
> On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote:
> > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> > > From: Sean Wang
> > >
> > > Since the offset for both registers,
On Sat, Mar 03, 2018 at 06:34:50AM +0800, Sean Wang wrote:
> On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote:
> > On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> > > From: Sean Wang
> > >
> > > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote:
> On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> > control PWM4 or PWM5 are distinct from
On Fri, 2018-03-02 at 11:57 +0100, Thierry Reding wrote:
> On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> > control PWM4 or PWM5 are distinct from the other PWMs, whose
On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes
On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes waveform cannot be output
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