Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
On 03/16/2018 09:36 PM, Stephen Boyd wrote: > Quoting sean.w...@mediatek.com (2018-02-17 11:54:36) >> From: Sean Wang>> >> All ethsys, pciesys and ssusbsys internally include reset controller, so >> explicitly add back these missing cell definitions to related bindings >> and examples. >> >> Signed-off-by: Sean Wang >> Cc: Rob Herring >> Cc: Michael Turquette >> Cc: Stephen Boyd >> Cc: linux-...@vger.kernel.org >> Reviewed-by: Rob Herring >> --- > > Acked-by: Stephen Boyd > added to v4.16-next/dts64 Thanks!
Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
On 03/16/2018 09:36 PM, Stephen Boyd wrote: > Quoting sean.w...@mediatek.com (2018-02-17 11:54:36) >> From: Sean Wang >> >> All ethsys, pciesys and ssusbsys internally include reset controller, so >> explicitly add back these missing cell definitions to related bindings >> and examples. >> >> Signed-off-by: Sean Wang >> Cc: Rob Herring >> Cc: Michael Turquette >> Cc: Stephen Boyd >> Cc: linux-...@vger.kernel.org >> Reviewed-by: Rob Herring >> --- > > Acked-by: Stephen Boyd > added to v4.16-next/dts64 Thanks!
Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
Quoting sean.w...@mediatek.com (2018-02-17 11:54:36) > From: Sean Wang> > All ethsys, pciesys and ssusbsys internally include reset controller, so > explicitly add back these missing cell definitions to related bindings > and examples. > > Signed-off-by: Sean Wang > Cc: Rob Herring > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: linux-...@vger.kernel.org > Reviewed-by: Rob Herring > --- Acked-by: Stephen Boyd
Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
Quoting sean.w...@mediatek.com (2018-02-17 11:54:36) > From: Sean Wang > > All ethsys, pciesys and ssusbsys internally include reset controller, so > explicitly add back these missing cell definitions to related bindings > and examples. > > Signed-off-by: Sean Wang > Cc: Rob Herring > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: linux-...@vger.kernel.org > Reviewed-by: Rob Herring > --- Acked-by: Stephen Boyd
Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote: > From: Sean Wang> > All ethsys, pciesys and ssusbsys internally include reset controller, so > explicitly add back these missing cell definitions to related bindings > and examples. > > Signed-off-by: Sean Wang > Cc: Rob Herring > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: linux-...@vger.kernel.org > Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger > --- > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + > Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ > Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ > 3 files changed, 5 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > index 6cc7840..8f5335b 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > @@ -9,6 +9,7 @@ Required Properties: > - "mediatek,mt2701-ethsys", "syscon" > - "mediatek,mt7622-ethsys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The ethsys controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > index d5d5f12..7fe5dc6 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be: > - "mediatek,mt7622-pciesys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The PCIESYS controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { > compatible = "mediatek,mt7622-pciesys", "syscon"; > reg = <0 0x1a100800 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > index 00760019..b8184da 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be: > - "mediatek,mt7622-ssusbsys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The SSUSBSYS controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a00 { > compatible = "mediatek,mt7622-ssusbsys", "syscon"; > reg = <0 0x1a00 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; >
Re: [PATCH v3 01/15] dt-bindings: clock: mediatek: add missing required #reset-cells
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote: > From: Sean Wang > > All ethsys, pciesys and ssusbsys internally include reset controller, so > explicitly add back these missing cell definitions to related bindings > and examples. > > Signed-off-by: Sean Wang > Cc: Rob Herring > Cc: Michael Turquette > Cc: Stephen Boyd > Cc: linux-...@vger.kernel.org > Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger > --- > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + > Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ > Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ > 3 files changed, 5 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > index 6cc7840..8f5335b 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > @@ -9,6 +9,7 @@ Required Properties: > - "mediatek,mt2701-ethsys", "syscon" > - "mediatek,mt7622-ethsys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The ethsys controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > index d5d5f12..7fe5dc6 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be: > - "mediatek,mt7622-pciesys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The PCIESYS controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { > compatible = "mediatek,mt7622-pciesys", "syscon"; > reg = <0 0x1a100800 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > index 00760019..b8184da 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be: > - "mediatek,mt7622-ssusbsys", "syscon" > - #clock-cells: Must be 1 > +- #reset-cells: Must be 1 > > The SSUSBSYS controller uses the common clk binding from > Documentation/devicetree/bindings/clock/clock-bindings.txt > @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a00 { > compatible = "mediatek,mt7622-ssusbsys", "syscon"; > reg = <0 0x1a00 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; >