On 9/13/2019 6:12 PM, andriy.shevche...@intel.com wrote:
On Fri, Sep 13, 2019 at 05:20:26PM +0800, Dilip Kota wrote:
On 9/12/2019 6:49 PM, Gustavo Pimentel wrote:
On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
wrote:
Hi, I just return from parental leave, therefore I still trying to get
the pa
On Fri, Sep 13, 2019 at 05:20:26PM +0800, Dilip Kota wrote:
> On 9/12/2019 6:49 PM, Gustavo Pimentel wrote:
> > On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
> > wrote:
> > Hi, I just return from parental leave, therefore I still trying to get
> > the pace in mailing list discussion.
> >
> > Howe
On 9/12/2019 6:49 PM, Gustavo Pimentel wrote:
On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
wrote:
Quoting Andrew Murray:
Quoting Gustavo Pimentel:
On 9/12/2019 4:25 PM, Andrew Murray wrote:
[...]
+static void intel_pcie_max_link_width_setup(struct intel_pcie_port *lpp)
+{
+ u32 mask
On Thu, Sep 12, 2019 at 10:23:31, Dilip Kota
wrote:
> Quoting Andrew Murray:
> Quoting Gustavo Pimentel:
>
> On 9/12/2019 4:25 PM, Andrew Murray wrote:
> > [...]
> >> +static void intel_pcie_max_link_width_setup(struct
> >> intel_pcie_port *lpp)
> >> +{
> >> +
Quoting Andrew Murray:
Quoting Gustavo Pimentel:
On 9/12/2019 4:25 PM, Andrew Murray wrote:
[...]
+static void intel_pcie_max_link_width_setup(struct intel_pcie_port *lpp)
+{
+ u32 mask, val;
+
+ /* HW auto bandwidth negotiation must be enabled */
+ pcie_rc_cfg_wr_mask(lpp, PC
On Thu, Sep 12, 2019 at 02:58:45PM +0800, Dilip Kota wrote:
> Hi Andrew Murray,
>
> On 9/11/2019 6:30 PM, Andrew Murray wrote:
> > On Tue, Sep 10, 2019 at 03:46:17PM +0800, Dilip Kota wrote:
> > > Hi Andrew Murray,
> > >
> > > Please find my response inline.
> > >
> > > On 9/9/2019 4:31 PM, Andr
Hi Andy,
On 9/5/2019 7:40 PM, Andy Shevchenko wrote:
On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci
Hi Andrew Murray,
On 9/11/2019 6:30 PM, Andrew Murray wrote:
On Tue, Sep 10, 2019 at 03:46:17PM +0800, Dilip Kota wrote:
Hi Andrew Murray,
Please find my response inline.
On 9/9/2019 4:31 PM, Andrew Murray wrote:
On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
On 9/6/2019 7:20 P
On Tue, Sep 10, 2019 at 03:46:17PM +0800, Dilip Kota wrote:
> Hi Andrew Murray,
>
> Please find my response inline.
>
> On 9/9/2019 4:31 PM, Andrew Murray wrote:
> > On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
> > > On 9/6/2019 7:20 PM, Andrew Murray wrote:
> > > > On Fri, Sep 06,
[Got delivery failure mail; so re-sending the mail]
Hi Andrew Murray,
Please find my response inline.
On 9/9/2019 4:31 PM, Andrew Murray wrote:
On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
On 9/6/2019 7:20 PM, Andrew Murray wrote:
On Fri, Sep 06, 2019 at 06:58:11PM +0800, Dili
On Mon, Sep 09, 2019 at 02:51:03PM +0800, Dilip Kota wrote:
>
> On 9/6/2019 7:20 PM, Andrew Murray wrote:
> > On Fri, Sep 06, 2019 at 06:58:11PM +0800, Dilip Kota wrote:
> > > Hi Andrew Murray,
> > >
> > > Thanks for the review. Please find my response inline.
> > >
> > > On 9/5/2019 6:45 PM, An
On 9/6/2019 7:20 PM, Andrew Murray wrote:
On Fri, Sep 06, 2019 at 06:58:11PM +0800, Dilip Kota wrote:
Hi Andrew Murray,
Thanks for the review. Please find my response inline.
On 9/5/2019 6:45 PM, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support t
On Fri, Sep 06, 2019 at 06:58:11PM +0800, Dilip Kota wrote:
> Hi Andrew Murray,
>
> Thanks for the review. Please find my response inline.
>
> On 9/5/2019 6:45 PM, Andrew Murray wrote:
> > On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
> > > Add support to PCIe RC controller on Intel
Hi Andrew Murray,
Thanks for the review. Please find my response inline.
On 9/5/2019 6:45 PM, Andrew Murray wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci c
Hi Andy,
Thanks for the review comments, please find my response inline.
On 9/4/2019 9:05 PM, Andy Shevchenko wrote:
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci
On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
> On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
> > Add support to PCIe RC controller on Intel Universal
> > Gateway SoC. PCIe controller is based of Synopsys
> > Designware pci core.
> > +config PCIE_INTEL_AXI
I think t
On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
> > +depends on OF
> > +select PCIE_DW_HOST
> > +help
> > + Say 'Y' here to enable support for Intel AHB/AXI PCIe Host
> > + controller driver.
> > + The Intel PCIe controller is based on the Syn
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Universal
> Gateway SoC. PCIe controller is based of Synopsys
> Designware pci core.
>
> Signed-off-by: Dilip Kota
> ---
Hi Dilip,
Thanks for the patch, initial feedback below:
> changes on
Hi Dilip,
On 9/4/2019 6:10 PM, Dilip Kota wrote:
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci core.
Signed-off-by: Dilip Kota
---
changes on v3:
Rename PCIe app logic registers with PCIE_APP prefix.
PCIE_I
On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Universal
> Gateway SoC. PCIe controller is based of Synopsys
> Designware pci core.
Thanks for an update. My comments below.
> +config PCIE_INTEL_AXI
> +bool "Intel AHB/AXI PCIe host
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