On Sat, 8 Sep 2018, Thomas Gleixner wrote:
> On Fri, 7 Sep 2018, Jiri Kosina wrote:
> > So I will go through the whole codepath again, but I fear your suggestion
> > would not work -- see the check for cpu_smt_control in stibp_needed(). We
> > need to see the old (or new, depending on the
On Sat, 8 Sep 2018, Thomas Gleixner wrote:
> On Fri, 7 Sep 2018, Jiri Kosina wrote:
> > So I will go through the whole codepath again, but I fear your suggestion
> > would not work -- see the check for cpu_smt_control in stibp_needed(). We
> > need to see the old (or new, depending on the
On Sat, 8 Sep 2018, Thomas Gleixner wrote:
> If after changing the SMT to enable a normal hotplug operation happens
> then you need to update the MSR as well.
Ah, right you are, thanks. Will fix in v5.
--
Jiri Kosina
SUSE Labs
On Sat, 8 Sep 2018, Thomas Gleixner wrote:
> If after changing the SMT to enable a normal hotplug operation happens
> then you need to update the MSR as well.
Ah, right you are, thanks. Will fix in v5.
--
Jiri Kosina
SUSE Labs
On Fri, 7 Sep 2018, Jiri Kosina wrote:
> On Fri, 7 Sep 2018, Thomas Gleixner wrote:
>
> > > + * The read-modify-write of the MSR doesn't need any race protection
> > > here,
> > > + * as we're running in atomic context.
> > > + */
> > > +static void enable_stibp(void *info)
> > > +{
> > > + u64
On Fri, 7 Sep 2018, Jiri Kosina wrote:
> On Fri, 7 Sep 2018, Thomas Gleixner wrote:
>
> > > + * The read-modify-write of the MSR doesn't need any race protection
> > > here,
> > > + * as we're running in atomic context.
> > > + */
> > > +static void enable_stibp(void *info)
> > > +{
> > > + u64
On Fri, 7 Sep 2018, Thomas Gleixner wrote:
> > + * The read-modify-write of the MSR doesn't need any race protection here,
> > + * as we're running in atomic context.
> > + */
> > +static void enable_stibp(void *info)
> > +{
> > + u64 mask;
> > + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> > + mask
On Fri, 7 Sep 2018, Thomas Gleixner wrote:
> > + * The read-modify-write of the MSR doesn't need any race protection here,
> > + * as we're running in atomic context.
> > + */
> > +static void enable_stibp(void *info)
> > +{
> > + u64 mask;
> > + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> > + mask
On Thu, 6 Sep 2018, Jiri Kosina wrote:
> +/*
> + * The read-modify-write of the MSR doesn't need any race protection here,
> + * as we're running in atomic context.
> + */
> +static void enable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> + mask |=
On Thu, 6 Sep 2018, Jiri Kosina wrote:
> +/*
> + * The read-modify-write of the MSR doesn't need any race protection here,
> + * as we're running in atomic context.
> + */
> +static void enable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
> + mask |=
On Thu, Sep 06, 2018 at 10:33:39AM +0200, Jiri Kosina wrote:
> +/*
> + * The read-modify-write of the MSR doesn't need any race protection here,
> + * as we're running in atomic context.
> + */
> +static void enable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
On Thu, Sep 06, 2018 at 10:33:39AM +0200, Jiri Kosina wrote:
> +/*
> + * The read-modify-write of the MSR doesn't need any race protection here,
> + * as we're running in atomic context.
> + */
> +static void enable_stibp(void *info)
> +{
> + u64 mask;
> + rdmsrl(MSR_IA32_SPEC_CTRL, mask);
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