Re: [PATCH v6 05/11] x86: add SGX MSRs to msr-index.h

2017-11-28 Thread Jarkko Sakkinen 
On Tue, Nov 28, 2017 at 09:22:48AM -0800, Sean Christopherson wrote:
> On Sat, 2017-11-25 at 21:29 +0200, Jarkko Sakkinen wrote:
> > From: Haim Cohen 
> > 
> > These MSRs hold the SHA256 checksum of the currently configured root
> > key for enclave signatures.
> 
> The commit message doesn't talk about the launch control bit in the
> feature control MSR.

Correct, would make sense to refine this further.

/Jarkko

Re: [PATCH v6 05/11] x86: add SGX MSRs to msr-index.h

2017-11-28 Thread Jarkko Sakkinen 
On Tue, Nov 28, 2017 at 09:22:48AM -0800, Sean Christopherson wrote:
> On Sat, 2017-11-25 at 21:29 +0200, Jarkko Sakkinen wrote:
> > From: Haim Cohen 
> > 
> > These MSRs hold the SHA256 checksum of the currently configured root
> > key for enclave signatures.
> 
> The commit message doesn't talk about the launch control bit in the
> feature control MSR.

Correct, would make sense to refine this further.

/Jarkko

Re: [PATCH v6 05/11] x86: add SGX MSRs to msr-index.h

2017-11-28 Thread Sean Christopherson 
On Sat, 2017-11-25 at 21:29 +0200, Jarkko Sakkinen wrote:
> From: Haim Cohen 
> 
> These MSRs hold the SHA256 checksum of the currently configured root
> key for enclave signatures.

The commit message doesn't talk about the launch control bit in the
feature control MSR.

> 
> Signed-off-by: Haim Cohen 
> Signed-off-by: Jarkko Sakkinen 
> ---
>  arch/x86/include/asm/msr-index.h | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index b35cb98b5d60..22e27d46d046 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -436,6 +436,7 @@
>  #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
>  #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX(1<<2)
>  #define FEATURE_CONTROL_SGX_ENABLE  (1<<18)
> +#define FEATURE_CONTROL_SGX_LAUNCH_CONTROL_ENABLE(1<<17)
>  #define FEATURE_CONTROL_LMCE (1<<20)
>  
>  #define MSR_IA32_APICBASE0x001b
> @@ -502,6 +503,12 @@
>  #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
>  #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
>  
> +/* Intel SGX MSRs */
> +#define MSR_IA32_SGXLEPUBKEYHASH00x008C
> +#define MSR_IA32_SGXLEPUBKEYHASH10x008D
> +#define MSR_IA32_SGXLEPUBKEYHASH20x008E
> +#define MSR_IA32_SGXLEPUBKEYHASH30x008F
> +
>  /* Thermal Thresholds Support */
>  #define THERM_INT_THRESHOLD0_ENABLE(1 << 15)
>  #define THERM_SHIFT_THRESHOLD08

Re: [PATCH v6 05/11] x86: add SGX MSRs to msr-index.h

2017-11-28 Thread Sean Christopherson 
On Sat, 2017-11-25 at 21:29 +0200, Jarkko Sakkinen wrote:
> From: Haim Cohen 
> 
> These MSRs hold the SHA256 checksum of the currently configured root
> key for enclave signatures.

The commit message doesn't talk about the launch control bit in the
feature control MSR.

> 
> Signed-off-by: Haim Cohen 
> Signed-off-by: Jarkko Sakkinen 
> ---
>  arch/x86/include/asm/msr-index.h | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index b35cb98b5d60..22e27d46d046 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -436,6 +436,7 @@
>  #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
>  #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX(1<<2)
>  #define FEATURE_CONTROL_SGX_ENABLE  (1<<18)
> +#define FEATURE_CONTROL_SGX_LAUNCH_CONTROL_ENABLE(1<<17)
>  #define FEATURE_CONTROL_LMCE (1<<20)
>  
>  #define MSR_IA32_APICBASE0x001b
> @@ -502,6 +503,12 @@
>  #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
>  #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
>  
> +/* Intel SGX MSRs */
> +#define MSR_IA32_SGXLEPUBKEYHASH00x008C
> +#define MSR_IA32_SGXLEPUBKEYHASH10x008D
> +#define MSR_IA32_SGXLEPUBKEYHASH20x008E
> +#define MSR_IA32_SGXLEPUBKEYHASH30x008F
> +
>  /* Thermal Thresholds Support */
>  #define THERM_INT_THRESHOLD0_ENABLE(1 << 15)
>  #define THERM_SHIFT_THRESHOLD08