Re: [PATCH v8 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
hi, On Fri, 2015-09-18 at 12:12 +0530, Kishon Vijay Abraham I wrote: > Hi, > > On Wednesday 16 September 2015 12:14 PM, Chunfeng Yun wrote: > > support usb3.0 phy of mt65xx SoCs > few nitpicks: > > change $subject. This driver is no longer in usb directory. > > It can be just "phy: add usb3.0 phy driver for mt65xx SoCs". Ok > > > > Signed-off-by: Chunfeng Yun > > --- > > drivers/phy/Kconfig | 9 + > > drivers/phy/Makefile | 1 + > > drivers/phy/phy-mt65xx-usb3.c | 456 > > ++ > > 3 files changed, 466 insertions(+) > > create mode 100644 drivers/phy/phy-mt65xx-usb3.c > > > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > > index 47da573..ec436c1 100644 > > --- a/drivers/phy/Kconfig > > +++ b/drivers/phy/Kconfig > > @@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA > > help > > Support for SATA PHY on Hisilicon hix5hd2 Soc. > > > > +config PHY_MT65XX_USB3 > > + tristate "Mediatek USB3.0 PHY Driver" > > + depends on ARCH_MEDIATEK && OF > > + select GENERIC_PHY > > + help > > + Say 'Y' here to add support for Mediatek USB3.0 PHY driver > > + for mt65xx SoCs. it supports two usb2.0 ports and > > + one usb3.0 port. > > + > > config PHY_SUN4I_USB > > tristate "Allwinner sunxi SoC USB PHY driver" > > depends on ARCH_SUNXI && HAS_IOMEM && OF > > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > > index a5b18c1..a7cc629 100644 > > --- a/drivers/phy/Makefile > > +++ b/drivers/phy/Makefile > > @@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3)+= > > phy-ti-pipe3.o > > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o > > obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o > > obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o > > +obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o > > obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o > > obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o > > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o > > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c > > new file mode 100644 > > index 000..1f00b05 > > --- /dev/null > > +++ b/drivers/phy/phy-mt65xx-usb3.c > > @@ -0,0 +1,456 @@ > > +/* > > + * Copyright (c) 2015 MediaTek Inc. > > + * Author: Chunfeng Yun > > + * > > + * This software is licensed under the terms of the GNU General Public > > + * License version 2, as published by the Free Software Foundation, and > > + * may be copied, distributed, and modified under those terms. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * for sifslv2 register, but exclude port's; > > + * relative to USB3_SIF2_BASE base address > > + */ > > +#define SSUSB_SIFSLV_SPLLC 0x > > + > > +/* offsets of sub-segment in each port registers */ > > +#define SSUSB_SIFSLV_U2PHY_COM_BASE0x > > +#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100 > > +#define SSUSB_USB30_PHYA_SIV_B_BASE0x0300 > > +#define SSUSB_SIFSLV_U3PHYA_DA_BASE0x0400 > > + > > +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x) > > +#define PA0_RG_U2PLL_FORCE_ON BIT(15) > > + > > +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008) > > +#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) > > + > > +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014) > > +#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) > > +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) > > +#define PA5_RG_U2_HS_100U_U3_ENBIT(11) > > + > > +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018) > > +#define PA6_RG_U2_ISO_EN BIT(31) > > +#define PA6_RG_U2_BC11_SW_EN BIT(23) > > +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) > > + > > +#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020) > > +#define P2C_RG_USB20_GPIO_CTL BIT(9) > > +#define P2C_USB20_GPIO_MODEBIT(8) > > +#define P2C_U2_GPIO_CTR_MSK(P2C_RG_USB20_GPIO_CTL | > > P2C_USB20_GPIO_MODE) > > + > > +#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060) > > +#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) > > + > > +#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068) > > +#define P2C_FORCE_UART_EN BIT(26) > > +#define P2C_FORCE_DATAIN BIT(23) > > +#define P2C_FORCE_DM_PULLDOWN BIT(21) > > +#define P2C_FORCE_DP_PULLDOWN BIT(20) > > +#define P2C_FORCE_XCVRSEL BIT(19)
Re: [PATCH v8 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
hi, On Fri, 2015-09-18 at 12:12 +0530, Kishon Vijay Abraham I wrote: > Hi, > > On Wednesday 16 September 2015 12:14 PM, Chunfeng Yun wrote: > > support usb3.0 phy of mt65xx SoCs > few nitpicks: > > change $subject. This driver is no longer in usb directory. > > It can be just "phy: add usb3.0 phy driver for mt65xx SoCs". Ok > > > > Signed-off-by: Chunfeng Yun> > --- > > drivers/phy/Kconfig | 9 + > > drivers/phy/Makefile | 1 + > > drivers/phy/phy-mt65xx-usb3.c | 456 > > ++ > > 3 files changed, 466 insertions(+) > > create mode 100644 drivers/phy/phy-mt65xx-usb3.c > > > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > > index 47da573..ec436c1 100644 > > --- a/drivers/phy/Kconfig > > +++ b/drivers/phy/Kconfig > > @@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA > > help > > Support for SATA PHY on Hisilicon hix5hd2 Soc. > > > > +config PHY_MT65XX_USB3 > > + tristate "Mediatek USB3.0 PHY Driver" > > + depends on ARCH_MEDIATEK && OF > > + select GENERIC_PHY > > + help > > + Say 'Y' here to add support for Mediatek USB3.0 PHY driver > > + for mt65xx SoCs. it supports two usb2.0 ports and > > + one usb3.0 port. > > + > > config PHY_SUN4I_USB > > tristate "Allwinner sunxi SoC USB PHY driver" > > depends on ARCH_SUNXI && HAS_IOMEM && OF > > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > > index a5b18c1..a7cc629 100644 > > --- a/drivers/phy/Makefile > > +++ b/drivers/phy/Makefile > > @@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3)+= > > phy-ti-pipe3.o > > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o > > obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o > > obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o > > +obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o > > obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o > > obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o > > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o > > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c > > new file mode 100644 > > index 000..1f00b05 > > --- /dev/null > > +++ b/drivers/phy/phy-mt65xx-usb3.c > > @@ -0,0 +1,456 @@ > > +/* > > + * Copyright (c) 2015 MediaTek Inc. > > + * Author: Chunfeng Yun > > + * > > + * This software is licensed under the terms of the GNU General Public > > + * License version 2, as published by the Free Software Foundation, and > > + * may be copied, distributed, and modified under those terms. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* > > + * for sifslv2 register, but exclude port's; > > + * relative to USB3_SIF2_BASE base address > > + */ > > +#define SSUSB_SIFSLV_SPLLC 0x > > + > > +/* offsets of sub-segment in each port registers */ > > +#define SSUSB_SIFSLV_U2PHY_COM_BASE0x > > +#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100 > > +#define SSUSB_USB30_PHYA_SIV_B_BASE0x0300 > > +#define SSUSB_SIFSLV_U3PHYA_DA_BASE0x0400 > > + > > +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x) > > +#define PA0_RG_U2PLL_FORCE_ON BIT(15) > > + > > +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008) > > +#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) > > + > > +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014) > > +#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) > > +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) > > +#define PA5_RG_U2_HS_100U_U3_ENBIT(11) > > + > > +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018) > > +#define PA6_RG_U2_ISO_EN BIT(31) > > +#define PA6_RG_U2_BC11_SW_EN BIT(23) > > +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) > > + > > +#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020) > > +#define P2C_RG_USB20_GPIO_CTL BIT(9) > > +#define P2C_USB20_GPIO_MODEBIT(8) > > +#define P2C_U2_GPIO_CTR_MSK(P2C_RG_USB20_GPIO_CTL | > > P2C_USB20_GPIO_MODE) > > + > > +#define U3D_U2PHYDCR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060) > > +#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) > > + > > +#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068) > > +#define P2C_FORCE_UART_EN BIT(26) > > +#define P2C_FORCE_DATAIN BIT(23) > > +#define P2C_FORCE_DM_PULLDOWN BIT(21) > > +#define P2C_FORCE_DP_PULLDOWN
Re: [PATCH v8 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
Hi, On Wednesday 16 September 2015 12:14 PM, Chunfeng Yun wrote: > support usb3.0 phy of mt65xx SoCs few nitpicks: change $subject. This driver is no longer in usb directory. It can be just "phy: add usb3.0 phy driver for mt65xx SoCs". > > Signed-off-by: Chunfeng Yun > --- > drivers/phy/Kconfig | 9 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-mt65xx-usb3.c | 456 > ++ > 3 files changed, 466 insertions(+) > create mode 100644 drivers/phy/phy-mt65xx-usb3.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 47da573..ec436c1 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA > help > Support for SATA PHY on Hisilicon hix5hd2 Soc. > > +config PHY_MT65XX_USB3 > + tristate "Mediatek USB3.0 PHY Driver" > + depends on ARCH_MEDIATEK && OF > + select GENERIC_PHY > + help > + Say 'Y' here to add support for Mediatek USB3.0 PHY driver > + for mt65xx SoCs. it supports two usb2.0 ports and > + one usb3.0 port. > + > config PHY_SUN4I_USB > tristate "Allwinner sunxi SoC USB PHY driver" > depends on ARCH_SUNXI && HAS_IOMEM && OF > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index a5b18c1..a7cc629 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3) += > phy-ti-pipe3.o > obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o > obj-$(CONFIG_PHY_EXYNOS5250_SATA)+= phy-exynos5250-sata.o > obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o > +obj-$(CONFIG_PHY_MT65XX_USB3)+= phy-mt65xx-usb3.o > obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o > obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c > new file mode 100644 > index 000..1f00b05 > --- /dev/null > +++ b/drivers/phy/phy-mt65xx-usb3.c > @@ -0,0 +1,456 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Chunfeng Yun > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * for sifslv2 register, but exclude port's; > + * relative to USB3_SIF2_BASE base address > + */ > +#define SSUSB_SIFSLV_SPLLC 0x > + > +/* offsets of sub-segment in each port registers */ > +#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x > +#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100 > +#define SSUSB_USB30_PHYA_SIV_B_BASE 0x0300 > +#define SSUSB_SIFSLV_U3PHYA_DA_BASE 0x0400 > + > +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x) > +#define PA0_RG_U2PLL_FORCE_ONBIT(15) > + > +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008) > +#define PA2_RG_SIF_U2PLL_FORCE_ENBIT(18) > + > +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014) > +#define PA5_RG_U2_HSTX_SRCTRLGENMASK(14, 12) > +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) > +#define PA5_RG_U2_HS_100U_U3_EN BIT(11) > + > +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018) > +#define PA6_RG_U2_ISO_EN BIT(31) > +#define PA6_RG_U2_BC11_SW_EN BIT(23) > +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) > + > +#define U3P_U2PHYACR4(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020) > +#define P2C_RG_USB20_GPIO_CTLBIT(9) > +#define P2C_USB20_GPIO_MODE BIT(8) > +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) > + > +#define U3D_U2PHYDCR0(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060) > +#define P2C_RG_SIF_U2PLL_FORCE_ONBIT(24) > + > +#define U3P_U2PHYDTM0(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068) > +#define P2C_FORCE_UART_ENBIT(26) > +#define P2C_FORCE_DATAIN BIT(23) > +#define P2C_FORCE_DM_PULLDOWNBIT(21) > +#define P2C_FORCE_DP_PULLDOWNBIT(20) > +#define P2C_FORCE_XCVRSELBIT(19) > +#define P2C_FORCE_SUSPENDM BIT(18) > +#define P2C_FORCE_TERMSELBIT(17) > +#define P2C_RG_DATAINGENMASK(13, 10) > +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) > +#define P2C_RG_DMPULLDOWNBIT(7) > +#define P2C_RG_DPPULLDOWN
Re: [PATCH v8 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs
Hi, On Wednesday 16 September 2015 12:14 PM, Chunfeng Yun wrote: > support usb3.0 phy of mt65xx SoCs few nitpicks: change $subject. This driver is no longer in usb directory. It can be just "phy: add usb3.0 phy driver for mt65xx SoCs". > > Signed-off-by: Chunfeng Yun> --- > drivers/phy/Kconfig | 9 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-mt65xx-usb3.c | 456 > ++ > 3 files changed, 466 insertions(+) > create mode 100644 drivers/phy/phy-mt65xx-usb3.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 47da573..ec436c1 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -206,6 +206,15 @@ config PHY_HIX5HD2_SATA > help > Support for SATA PHY on Hisilicon hix5hd2 Soc. > > +config PHY_MT65XX_USB3 > + tristate "Mediatek USB3.0 PHY Driver" > + depends on ARCH_MEDIATEK && OF > + select GENERIC_PHY > + help > + Say 'Y' here to add support for Mediatek USB3.0 PHY driver > + for mt65xx SoCs. it supports two usb2.0 ports and > + one usb3.0 port. > + > config PHY_SUN4I_USB > tristate "Allwinner sunxi SoC USB PHY driver" > depends on ARCH_SUNXI && HAS_IOMEM && OF > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index a5b18c1..a7cc629 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3) += > phy-ti-pipe3.o > obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o > obj-$(CONFIG_PHY_EXYNOS5250_SATA)+= phy-exynos5250-sata.o > obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o > +obj-$(CONFIG_PHY_MT65XX_USB3)+= phy-mt65xx-usb3.o > obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o > obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c > new file mode 100644 > index 000..1f00b05 > --- /dev/null > +++ b/drivers/phy/phy-mt65xx-usb3.c > @@ -0,0 +1,456 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Chunfeng Yun > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* > + * for sifslv2 register, but exclude port's; > + * relative to USB3_SIF2_BASE base address > + */ > +#define SSUSB_SIFSLV_SPLLC 0x > + > +/* offsets of sub-segment in each port registers */ > +#define SSUSB_SIFSLV_U2PHY_COM_BASE 0x > +#define SSUSB_SIFSLV_U3PHYD_BASE 0x0100 > +#define SSUSB_USB30_PHYA_SIV_B_BASE 0x0300 > +#define SSUSB_SIFSLV_U3PHYA_DA_BASE 0x0400 > + > +#define U3P_USBPHYACR0 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x) > +#define PA0_RG_U2PLL_FORCE_ONBIT(15) > + > +#define U3P_USBPHYACR2 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0008) > +#define PA2_RG_SIF_U2PLL_FORCE_ENBIT(18) > + > +#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0014) > +#define PA5_RG_U2_HSTX_SRCTRLGENMASK(14, 12) > +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) > +#define PA5_RG_U2_HS_100U_U3_EN BIT(11) > + > +#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018) > +#define PA6_RG_U2_ISO_EN BIT(31) > +#define PA6_RG_U2_BC11_SW_EN BIT(23) > +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) > + > +#define U3P_U2PHYACR4(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020) > +#define P2C_RG_USB20_GPIO_CTLBIT(9) > +#define P2C_USB20_GPIO_MODE BIT(8) > +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) > + > +#define U3D_U2PHYDCR0(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0060) > +#define P2C_RG_SIF_U2PLL_FORCE_ONBIT(24) > + > +#define U3P_U2PHYDTM0(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0068) > +#define P2C_FORCE_UART_ENBIT(26) > +#define P2C_FORCE_DATAIN BIT(23) > +#define P2C_FORCE_DM_PULLDOWNBIT(21) > +#define P2C_FORCE_DP_PULLDOWNBIT(20) > +#define P2C_FORCE_XCVRSELBIT(19) > +#define P2C_FORCE_SUSPENDM BIT(18) > +#define P2C_FORCE_TERMSELBIT(17) > +#define P2C_RG_DATAINGENMASK(13, 10) > +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) > +#define