On Tue, Jun 18, 2013 at 11:22:13AM +0100, Lorenzo Pieralisi wrote:
> On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
> > That'll trim down the driver to a point where I think you'll find it much
> > easier to get merged. :-)
> To start with I have to understand in which directory
On Tue, Jun 18, 2013 at 11:22:13AM +0100, Lorenzo Pieralisi wrote:
On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
That'll trim down the driver to a point where I think you'll find it much
easier to get merged. :-)
To start with I have to understand in which directory this
Hi,
On Tue, Jun 18, 2013 at 11:22:13AM +0100, Lorenzo Pieralisi wrote:
> Hi Olof,
>
> thanks a lot.
>
> On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
> >
> > Sorry, I got to think of this over the weekend and should have replied
> > before you had a chance to repost, but
Hi,
On Tue, Jun 18, 2013 at 11:22:13AM +0100, Lorenzo Pieralisi wrote:
Hi Olof,
thanks a lot.
On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
Sorry, I got to think of this over the weekend and should have replied
before you had a chance to repost, but still:
Why
On Tue, Jun 18, 2013 at 05:25:22AM +0100, Nicolas Pitre wrote:
> On Mon, 17 Jun 2013, Lorenzo Pieralisi wrote:
>
> > The TC2 versatile express core tile integrates a logic block that provides
> > the
> > interface between the dual cluster test-chip and the M3 microcontroller that
> > carries out
Hi Olof,
thanks a lot.
On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
> On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
> > The TC2 versatile express core tile integrates a logic block that provides
> > the
> > interface between the dual cluster test-chip and
Hi Olof,
On Mon, Jun 17, 2013 at 10:44:51AM -0700, Olof Johansson wrote:
> On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
> > The TC2 versatile express core tile integrates a logic block that provides
> > the
> > interface between the dual cluster test-chip and the M3
Hi Olof,
thanks a lot.
On Mon, Jun 17, 2013 at 06:44:51PM +0100, Olof Johansson wrote:
On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test-chip and the M3
On Tue, Jun 18, 2013 at 05:25:22AM +0100, Nicolas Pitre wrote:
On Mon, 17 Jun 2013, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power
Hi Olof,
On Mon, Jun 17, 2013 at 10:44:51AM -0700, Olof Johansson wrote:
On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides
the
interface between the dual cluster test-chip and the M3
On Mon, 17 Jun 2013, Lorenzo Pieralisi wrote:
> The TC2 versatile express core tile integrates a logic block that provides the
> interface between the dual cluster test-chip and the M3 microcontroller that
> carries out power management. The logic block, called Serial Power Controller
> (SPC),
On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
> The TC2 versatile express core tile integrates a logic block that provides the
> interface between the dual cluster test-chip and the M3 microcontroller that
> carries out power management. The logic block, called Serial Power
On Mon, Jun 17, 2013 at 04:51:09PM +0100, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power
On Mon, 17 Jun 2013, Lorenzo Pieralisi wrote:
The TC2 versatile express core tile integrates a logic block that provides the
interface between the dual cluster test-chip and the M3 microcontroller that
carries out power management. The logic block, called Serial Power Controller
(SPC),
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