On 03/12/2018 10:06 AM, Andy Lutomirski wrote:
> I'd be surprised if there's a noticeable performance hit on anything
> except the micro-est of benchmarks. We're talking one extra
> intermediate paging structure cache entry in use, maybe a few data
> cache lines, and (wild guess) 0 extra cycles on
* Linus Torvalds wrote:
> But regardless, I think we're better off with a "wait and see" approach.
>
> IOW, try to use 5-level whenever possible for now, and _if_ somebody actually
> can show that 4-level page tables perform better or have some other
> advantage,
> we can then try to be clev
On Mon, Mar 12, 2018 at 10:06 AM, Andy Lutomirski wrote:
>
> I'd be surprised if there's a noticeable performance hit on anything
> except the micro-est of benchmarks. We're talking one extra
> intermediate paging structure cache entry in use, maybe a few data
> cache lines, and (wild guess) 0 ex
On Mon, Mar 12, 2018 at 4:42 PM, Linus Torvalds
wrote:
> On Mon, Mar 12, 2018 at 7:50 AM, Kirill A. Shutemov
> wrote:
>>
>> I disagree that we should decide usefulness of the 5-level paging based on
>> size of physical memory on the machine.
>>
>> Consider use case when you have 100TiB database f
On Mon, Mar 12, 2018 at 7:50 AM, Kirill A. Shutemov
wrote:
>
> I disagree that we should decide usefulness of the 5-level paging based on
> size of physical memory on the machine.
>
> Consider use case when you have 100TiB database file. It's pretty
> reasonable to mmap() such file at once even if
On Mon, Mar 12, 2018 at 03:32:12PM +0100, Ingo Molnar wrote:
>
> * Kirill A. Shutemov wrote:
>
> > > We can of course bike shed / benchmark this once my desktop refresh
> > > sports this feature, but ISTR this being one of the very first things
> > > Ingo mentioned when we started this whole 5L
On Mon, Mar 12, 2018 at 02:32:12PM +, Ingo Molnar wrote:
>
> * Kirill A. Shutemov wrote:
>
> > > We can of course bike shed / benchmark this once my desktop refresh
> > > sports this feature, but ISTR this being one of the very first things
> > > Ingo mentioned when we started this whole 5L
* Kirill A. Shutemov wrote:
> > We can of course bike shed / benchmark this once my desktop refresh
> > sports this feature, but ISTR this being one of the very first things
> > Ingo mentioned when we started this whole 5L thing.
>
> I would rather not fix the problem that may not actually exis
On Mon, Mar 12, 2018 at 02:10:55PM +0100, Peter Zijlstra wrote:
> On Mon, Mar 12, 2018 at 03:43:37PM +0300, Kirill A. Shutemov wrote:
> > On Mon, Mar 12, 2018 at 01:40:27PM +0100, Peter Zijlstra wrote:
> > > On Mon, Mar 12, 2018 at 02:27:58AM -0700, tip-bot for Kirill A. Shutemov
> > > wrote:
> >
On Mon, Mar 12, 2018 at 03:43:37PM +0300, Kirill A. Shutemov wrote:
> On Mon, Mar 12, 2018 at 01:40:27PM +0100, Peter Zijlstra wrote:
> > On Mon, Mar 12, 2018 at 02:27:58AM -0700, tip-bot for Kirill A. Shutemov
> > wrote:
> > > + /*
> > > + * Check if LA57 is desired and supported.
> > > + *
> >
On Mon, Mar 12, 2018 at 01:40:27PM +0100, Peter Zijlstra wrote:
> On Mon, Mar 12, 2018 at 02:27:58AM -0700, tip-bot for Kirill A. Shutemov
> wrote:
> > + /*
> > +* Check if LA57 is desired and supported.
> > +*
> > +* There are two parts to the check:
> > +* - if the kernel sup
On Mon, Mar 12, 2018 at 02:27:58AM -0700, tip-bot for Kirill A. Shutemov wrote:
> + /*
> + * Check if LA57 is desired and supported.
> + *
> + * There are two parts to the check:
> + * - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
> + * - if the machi
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