Re: [v3 PATCH 3/3] powernv-cpufreq: Treat pstates as opaque 8-bit values

Hi Balbir, On Sun, Dec 17, 2017 at 02:17:02PM +1100, Balbir Singh wrote: > On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy [..snip..] > > > > -static inline int extract_pstate(u64 pmsr_val, unsigned int shift) > > +static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift) > > { > > -

Re: [v3 PATCH 3/3] powernv-cpufreq: Treat pstates as opaque 8-bit values

Hi Balbir, On Sun, Dec 17, 2017 at 02:17:02PM +1100, Balbir Singh wrote: > On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy [..snip..] > > > > -static inline int extract_pstate(u64 pmsr_val, unsigned int shift) > > +static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift) > > { > > -

Re: [v3 PATCH 3/3] powernv-cpufreq: Treat pstates as opaque 8-bit values

On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > On POWER8 and POWER9, the PMSR and the PMCR registers define pstates > to be 8-bit wide values. The device-tree exports pstates as 32-bit > wide values of

Re: [v3 PATCH 3/3] powernv-cpufreq: Treat pstates as opaque 8-bit values

On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > On POWER8 and POWER9, the PMSR and the PMCR registers define pstates > to be 8-bit wide values. The device-tree exports pstates as 32-bit > wide values of which the lower byte is the actual pstate. > > The