tree: https://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git for-next head: a9f947bb3dc755158f69eea147d2ea92e3e4dcfe commit: c7088cea971e9fff1027861025778ab016a16c30 [14/15] m68k: remove local __raw_read/__raw_write macros for non-MMU config: m68k-m5249evb_defconfig (attached as .config) compiler: m68k-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout c7088cea971e9fff1027861025778ab016a16c30 # save the attached .config to linux build tree make.cross ARCH=m68k
All warnings (new ones prefixed by >>):
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/include/asm/gpio.h:21,
from include/linux/gpio.h:59,
from arch/m68k/coldfire/device.c:15:
arch/m68k/coldfire/device.c: In function 'mcf_uart_set_irq':
>> arch/m68k/include/asm/m525xsim.h:46:22: warning: passing argument 2 of
>> 'writeb' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
^
>> arch/m68k/include/asm/m525xsim.h:148:26: note: in expansion of macro
>> 'MCFSIM_ICR4'
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
^~~~~~~~~~~
>> arch/m68k/coldfire/device.c:517:46: note: in expansion of macro
>> 'MCFSIM_UART1ICR'
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
^~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/device.c:13:
include/asm-generic/io.h:208:16: note: expected 'volatile void *' but
argument is of type 'int'
#define writeb writeb
^
include/asm-generic/io.h:209:20: note: in expansion of macro 'writeb'
static inline void writeb(u8 value, volatile void __iomem *addr)
^~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/include/asm/gpio.h:21,
from include/linux/gpio.h:59,
from arch/m68k/coldfire/device.c:15:
arch/m68k/include/asm/m525xsim.h:103:24: warning: passing argument 2 of
'writeb' makes pointer from integer without a cast [-Wint-conversion]
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
^
>> arch/m68k/coldfire/device.c:518:24: note: in expansion of macro
>> 'MCFUART_BASE0'
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
^~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/device.c:13:
include/asm-generic/io.h:208:16: note: expected 'volatile void *' but
argument is of type 'int'
#define writeb writeb
^
include/asm-generic/io.h:209:20: note: in expansion of macro 'writeb'
static inline void writeb(u8 value, volatile void __iomem *addr)
^~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/include/asm/gpio.h:21,
from include/linux/gpio.h:59,
from arch/m68k/coldfire/device.c:15:
arch/m68k/include/asm/m525xsim.h:47:22: warning: passing argument 2 of
'writeb' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
^
>> arch/m68k/include/asm/m525xsim.h:149:26: note: in expansion of macro
>> 'MCFSIM_ICR5'
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
^~~~~~~~~~~
>> arch/m68k/coldfire/device.c:522:46: note: in expansion of macro
>> 'MCFSIM_UART2ICR'
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
^~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/device.c:13:
include/asm-generic/io.h:208:16: note: expected 'volatile void *' but
argument is of type 'int'
#define writeb writeb
^
include/asm-generic/io.h:209:20: note: in expansion of macro 'writeb'
static inline void writeb(u8 value, volatile void __iomem *addr)
^~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/include/asm/gpio.h:21,
from include/linux/gpio.h:59,
from arch/m68k/coldfire/device.c:15:
arch/m68k/include/asm/m525xsim.h:104:24: warning: passing argument 2 of
'writeb' makes pointer from integer without a cast [-Wint-conversion]
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
^
>> arch/m68k/coldfire/device.c:523:24: note: in expansion of macro
>> 'MCFUART_BASE1'
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
^~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/device.c:13:
include/asm-generic/io.h:208:16: note: expected 'volatile void *' but
argument is of type 'int'
#define writeb writeb
^
include/asm-generic/io.h:209:20: note: in expansion of macro 'writeb'
static inline void writeb(u8 value, volatile void __iomem *addr)
^~~~~~
--
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/m5249.c:19:
arch/m68k/coldfire/m5249.c: In function 'm5249_smc91x_init':
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 1 of
>> '__raw_readl' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
>> arch/m68k/coldfire/m5249.c:120:15: note: in expansion of macro
>> 'MCFSIM2_GPIOINTENABLE'
gpio = readl(MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/m5249.c:15:
include/asm-generic/io.h:97:21: note: expected 'const volatile void *' but
argument is of type 'unsigned int'
#define __raw_readl __raw_readl
^
include/asm-generic/io.h:98:19: note: in expansion of macro '__raw_readl'
static inline u32 __raw_readl(const volatile void __iomem *addr)
^~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/m5249.c:19:
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 2 of
>> '__raw_writel' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
arch/m68k/coldfire/m5249.c:121:22: note: in expansion of macro
'MCFSIM2_GPIOINTENABLE'
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/m5249.c:15:
include/asm-generic/io.h:131:22: note: expected 'volatile void *' but
argument is of type 'unsigned int'
#define __raw_writel __raw_writel
^
include/asm-generic/io.h:132:20: note: in expansion of macro '__raw_writel'
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
^~~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/m5249.c:19:
arch/m68k/include/asm/m525xsim.h:85:26: warning: passing argument 1 of
'__raw_readl' makes pointer from integer without a cast [-Wint-conversion]
#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
^
>> arch/m68k/coldfire/m5249.c:123:15: note: in expansion of macro
>> 'MCFINTC2_INTPRI5'
gpio = readl(MCFINTC2_INTPRI5);
^~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/m5249.c:15:
include/asm-generic/io.h:97:21: note: expected 'const volatile void *' but
argument is of type 'unsigned int'
#define __raw_readl __raw_readl
^
include/asm-generic/io.h:98:19: note: in expansion of macro '__raw_readl'
static inline u32 __raw_readl(const volatile void __iomem *addr)
^~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/m5249.c:19:
arch/m68k/include/asm/m525xsim.h:85:26: warning: passing argument 2 of
'__raw_writel' makes pointer from integer without a cast [-Wint-conversion]
#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
^
arch/m68k/coldfire/m5249.c:124:28: note: in expansion of macro
'MCFINTC2_INTPRI5'
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
^~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from arch/m68k/coldfire/m5249.c:15:
include/asm-generic/io.h:131:22: note: expected 'volatile void *' but
argument is of type 'unsigned int'
#define __raw_writel __raw_writel
^
include/asm-generic/io.h:132:20: note: in expansion of macro '__raw_writel'
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
^~~~~~~~~~~~
--
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/intc-5249.c:18:
arch/m68k/coldfire/intc-5249.c: In function 'intc2_irq_gpio_mask':
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 1 of
>> '__raw_readl' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
>> arch/m68k/coldfire/intc-5249.c:23:14: note: in expansion of macro
>> 'MCFSIM2_GPIOINTENABLE'
imr = readl(MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:13,
from arch/m68k/include/asm/hardirq.h:25,
from include/linux/hardirq.h:9,
from include/linux/interrupt.h:11,
from arch/m68k/coldfire/intc-5249.c:14:
include/asm-generic/io.h:97:21: note: expected 'const volatile void *' but
argument is of type 'unsigned int'
#define __raw_readl __raw_readl
^
include/asm-generic/io.h:98:19: note: in expansion of macro '__raw_readl'
static inline u32 __raw_readl(const volatile void __iomem *addr)
^~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/intc-5249.c:18:
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 2 of
>> '__raw_writel' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
arch/m68k/coldfire/intc-5249.c:25:14: note: in expansion of macro
'MCFSIM2_GPIOINTENABLE'
writel(imr, MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:13,
from arch/m68k/include/asm/hardirq.h:25,
from include/linux/hardirq.h:9,
from include/linux/interrupt.h:11,
from arch/m68k/coldfire/intc-5249.c:14:
include/asm-generic/io.h:131:22: note: expected 'volatile void *' but
argument is of type 'unsigned int'
#define __raw_writel __raw_writel
^
include/asm-generic/io.h:132:20: note: in expansion of macro '__raw_writel'
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
^~~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/intc-5249.c:18:
arch/m68k/coldfire/intc-5249.c: In function 'intc2_irq_gpio_unmask':
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 1 of
>> '__raw_readl' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
arch/m68k/coldfire/intc-5249.c:31:14: note: in expansion of macro
'MCFSIM2_GPIOINTENABLE'
imr = readl(MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:13,
from arch/m68k/include/asm/hardirq.h:25,
from include/linux/hardirq.h:9,
from include/linux/interrupt.h:11,
from arch/m68k/coldfire/intc-5249.c:14:
include/asm-generic/io.h:97:21: note: expected 'const volatile void *' but
argument is of type 'unsigned int'
#define __raw_readl __raw_readl
^
include/asm-generic/io.h:98:19: note: in expansion of macro '__raw_readl'
static inline u32 __raw_readl(const volatile void __iomem *addr)
^~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/intc-5249.c:18:
>> arch/m68k/include/asm/m525xsim.h:200:31: warning: passing argument 2 of
>> '__raw_writel' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
^
arch/m68k/coldfire/intc-5249.c:33:14: note: in expansion of macro
'MCFSIM2_GPIOINTENABLE'
writel(imr, MCFSIM2_GPIOINTENABLE);
^~~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:13,
from arch/m68k/include/asm/hardirq.h:25,
from include/linux/hardirq.h:9,
from include/linux/interrupt.h:11,
from arch/m68k/coldfire/intc-5249.c:14:
include/asm-generic/io.h:131:22: note: expected 'volatile void *' but
argument is of type 'unsigned int'
#define __raw_writel __raw_writel
^
include/asm-generic/io.h:132:20: note: in expansion of macro '__raw_writel'
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
^~~~~~~~~~~~
In file included from arch/m68k/include/asm/mcfsim.h:29:0,
from arch/m68k/coldfire/intc-5249.c:18:
arch/m68k/coldfire/intc-5249.c: In function 'intc2_irq_gpio_ack':
arch/m68k/include/asm/m525xsim.h:199:30: warning: passing argument 2 of
'__raw_writel' makes pointer from integer without a cast [-Wint-conversion]
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
^
>> arch/m68k/coldfire/intc-5249.c:38:42: note: in expansion of macro
>> 'MCFSIM2_GPIOINTCLEAR'
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
^~~~~~~~~~~~~~~~~~~~
In file included from arch/m68k/include/asm/io_no.h:129:0,
from arch/m68k/include/asm/io.h:3,
from include/linux/io.h:25,
from include/linux/irq.h:20,
from include/asm-generic/hardirq.h:13,
from arch/m68k/include/asm/hardirq.h:25,
from include/linux/hardirq.h:9,
from include/linux/interrupt.h:11,
from arch/m68k/coldfire/intc-5249.c:14:
include/asm-generic/io.h:131:22: note: expected 'volatile void *' but
argument is of type 'unsigned int'
#define __raw_writel __raw_writel
^
include/asm-generic/io.h:132:20: note: in expansion of macro '__raw_writel'
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
^~~~~~~~~~~~
vim +/__raw_readl +200 arch/m68k/include/asm/m525xsim.h
04e037aa Steven King 2012-06-05 31
04e037aa Steven King 2012-06-05 32 /*
04e037aa Steven King 2012-06-05 33 * Define the 525x SIM register
set addresses.
04e037aa Steven King 2012-06-05 34 */
e1e362dc Greg Ungerer 2012-07-15 35 #define MCFSIM_RSR
(MCF_MBAR + 0x00) /* Reset Status */
e1e362dc Greg Ungerer 2012-07-15 36 #define MCFSIM_SYPCR
(MCF_MBAR + 0x01) /* System Protection */
660b73e3 Greg Ungerer 2012-07-15 37 #define MCFSIM_SWIVR
(MCF_MBAR + 0x02) /* SW Watchdog intr */
660b73e3 Greg Ungerer 2012-07-15 38 #define MCFSIM_SWSR
(MCF_MBAR + 0x03) /* SW Watchdog srv */
35142b91 Greg Ungerer 2012-09-14 39 #define MCFSIM_MPARK
(MCF_MBAR + 0x0C) /* BUS Master Ctrl */
6a3a786d Greg Ungerer 2012-07-15 40 #define MCFSIM_IPR
(MCF_MBAR + 0x40) /* Interrupt Pending */
6a3a786d Greg Ungerer 2012-07-15 41 #define MCFSIM_IMR
(MCF_MBAR + 0x44) /* Interrupt Mask */
c986a3d5 Greg Ungerer 2012-08-17 42 #define MCFSIM_ICR0
(MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
c986a3d5 Greg Ungerer 2012-08-17 43 #define MCFSIM_ICR1
(MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
c986a3d5 Greg Ungerer 2012-08-17 44 #define MCFSIM_ICR2
(MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
c986a3d5 Greg Ungerer 2012-08-17 45 #define MCFSIM_ICR3
(MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
c986a3d5 Greg Ungerer 2012-08-17 @46 #define MCFSIM_ICR4
(MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
c986a3d5 Greg Ungerer 2012-08-17 @47 #define MCFSIM_ICR5
(MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
c986a3d5 Greg Ungerer 2012-08-17 48 #define MCFSIM_ICR6
(MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
c986a3d5 Greg Ungerer 2012-08-17 49 #define MCFSIM_ICR7
(MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
c986a3d5 Greg Ungerer 2012-08-17 50 #define MCFSIM_ICR8
(MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
c986a3d5 Greg Ungerer 2012-08-17 51 #define MCFSIM_ICR9
(MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
c986a3d5 Greg Ungerer 2012-08-17 52 #define MCFSIM_ICR10
(MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
c986a3d5 Greg Ungerer 2012-08-17 53 #define MCFSIM_ICR11
(MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
04e037aa Steven King 2012-06-05 54
1419ea3b Greg Ungerer 2012-09-14 55 #define MCFSIM_CSAR0
(MCF_MBAR + 0x80) /* CS 0 Address reg */
1419ea3b Greg Ungerer 2012-09-14 56 #define MCFSIM_CSMR0
(MCF_MBAR + 0x84) /* CS 0 Mask reg */
1419ea3b Greg Ungerer 2012-09-14 57 #define MCFSIM_CSCR0
(MCF_MBAR + 0x8a) /* CS 0 Control reg */
1419ea3b Greg Ungerer 2012-09-14 58 #define MCFSIM_CSAR1
(MCF_MBAR + 0x8c) /* CS 1 Address reg */
1419ea3b Greg Ungerer 2012-09-14 59 #define MCFSIM_CSMR1
(MCF_MBAR + 0x90) /* CS 1 Mask reg */
1419ea3b Greg Ungerer 2012-09-14 60 #define MCFSIM_CSCR1
(MCF_MBAR + 0x96) /* CS 1 Control reg */
1419ea3b Greg Ungerer 2012-09-14 61 #define MCFSIM_CSAR2
(MCF_MBAR + 0x98) /* CS 2 Address reg */
1419ea3b Greg Ungerer 2012-09-14 62 #define MCFSIM_CSMR2
(MCF_MBAR + 0x9c) /* CS 2 Mask reg */
1419ea3b Greg Ungerer 2012-09-14 63 #define MCFSIM_CSCR2
(MCF_MBAR + 0xa2) /* CS 2 Control reg */
1419ea3b Greg Ungerer 2012-09-14 64 #define MCFSIM_CSAR3
(MCF_MBAR + 0xa4) /* CS 3 Address reg */
1419ea3b Greg Ungerer 2012-09-14 65 #define MCFSIM_CSMR3
(MCF_MBAR + 0xa8) /* CS 3 Mask reg */
1419ea3b Greg Ungerer 2012-09-14 66 #define MCFSIM_CSCR3
(MCF_MBAR + 0xae) /* CS 3 Control reg */
1419ea3b Greg Ungerer 2012-09-14 67 #define MCFSIM_CSAR4
(MCF_MBAR + 0xb0) /* CS 4 Address reg */
1419ea3b Greg Ungerer 2012-09-14 68 #define MCFSIM_CSMR4
(MCF_MBAR + 0xb4) /* CS 4 Mask reg */
1419ea3b Greg Ungerer 2012-09-14 69 #define MCFSIM_CSCR4
(MCF_MBAR + 0xba) /* CS 4 Control reg */
04e037aa Steven King 2012-06-05 70
04e037aa Steven King 2012-06-05 71 #define MCFSIM_DCR
(MCF_MBAR + 0x100) /* DRAM Control */
04e037aa Steven King 2012-06-05 72 #define MCFSIM_DACR0
(MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
04e037aa Steven King 2012-06-05 73 #define MCFSIM_DMR0
(MCF_MBAR + 0x10c) /* DRAM 0 Mask */
5a4acf3e Greg Ungerer 2012-09-19 74 #define MCFSIM_DACR1
(MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
5a4acf3e Greg Ungerer 2012-09-19 75 #define MCFSIM_DMR1
(MCF_MBAR + 0x114) /* DRAM 1 Mask */
04e037aa Steven King 2012-06-05 76
04e037aa Steven King 2012-06-05 77 /*
04e037aa Steven King 2012-06-05 78 * Secondary Interrupt Controller (in
MBAR2)
04e037aa Steven King 2012-06-05 79 */
04e037aa Steven King 2012-06-05 80 #define MCFINTC2_INTBASE
(MCF_MBAR2 + 0x168) /* Base Vector Reg */
04e037aa Steven King 2012-06-05 81 #define MCFINTC2_INTPRI1
(MCF_MBAR2 + 0x140) /* 0-7 priority */
04e037aa Steven King 2012-06-05 82 #define MCFINTC2_INTPRI2
(MCF_MBAR2 + 0x144) /* 8-15 priority */
04e037aa Steven King 2012-06-05 83 #define MCFINTC2_INTPRI3
(MCF_MBAR2 + 0x148) /* 16-23 priority */
04e037aa Steven King 2012-06-05 84 #define MCFINTC2_INTPRI4
(MCF_MBAR2 + 0x14c) /* 24-31 priority */
04e037aa Steven King 2012-06-05 85 #define MCFINTC2_INTPRI5
(MCF_MBAR2 + 0x150) /* 32-39 priority */
04e037aa Steven King 2012-06-05 86 #define MCFINTC2_INTPRI6
(MCF_MBAR2 + 0x154) /* 40-47 priority */
04e037aa Steven King 2012-06-05 87 #define MCFINTC2_INTPRI7
(MCF_MBAR2 + 0x158) /* 48-55 priority */
04e037aa Steven King 2012-06-05 88 #define MCFINTC2_INTPRI8
(MCF_MBAR2 + 0x15c) /* 56-63 priority */
04e037aa Steven King 2012-06-05 89
04e037aa Steven King 2012-06-05 90 #define MCFINTC2_INTPRI_REG(i)
(MCFINTC2_INTPRI1 + \
04e037aa Steven King 2012-06-05 91 ((((i)
- MCFINTC2_VECBASE) / 8) * 4))
04e037aa Steven King 2012-06-05 92 #define MCFINTC2_INTPRI_BITS(b, i)
((b) << (((i) % 8) * 4))
04e037aa Steven King 2012-06-05 93
04e037aa Steven King 2012-06-05 94 /*
04e037aa Steven King 2012-06-05 95 * Timer module.
04e037aa Steven King 2012-06-05 96 */
04e037aa Steven King 2012-06-05 97 #define MCFTIMER_BASE1
(MCF_MBAR + 0x140) /* Base of TIMER1 */
04e037aa Steven King 2012-06-05 98 #define MCFTIMER_BASE2
(MCF_MBAR + 0x180) /* Base of TIMER2 */
04e037aa Steven King 2012-06-05 99
04e037aa Steven King 2012-06-05 100 /*
04e037aa Steven King 2012-06-05 101 * UART module.
04e037aa Steven King 2012-06-05 102 */
04e037aa Steven King 2012-06-05 103 #define MCFUART_BASE0
(MCF_MBAR + 0x1c0) /* Base address UART0 */
04e037aa Steven King 2012-06-05 104 #define MCFUART_BASE1
(MCF_MBAR + 0x200) /* Base address UART1 */
04e037aa Steven King 2012-06-05 105
04e037aa Steven King 2012-06-05 106 /*
04e037aa Steven King 2012-06-05 107 * QSPI module.
04e037aa Steven King 2012-06-05 108 */
e93e91f2 Steven King 2014-05-14 109 #define MCFQSPI_BASE
(MCF_MBAR + 0x400) /* Base address QSPI */
04e037aa Steven King 2012-06-05 110 #define MCFQSPI_SIZE 0x40
/* Register set size */
04e037aa Steven King 2012-06-05 111
5a4acf3e Greg Ungerer 2012-09-19 112 #ifdef CONFIG_M5249
5a4acf3e Greg Ungerer 2012-09-19 113 #define MCFQSPI_CS0 29
5a4acf3e Greg Ungerer 2012-09-19 114 #define MCFQSPI_CS1 24
5a4acf3e Greg Ungerer 2012-09-19 115 #define MCFQSPI_CS2 21
5a4acf3e Greg Ungerer 2012-09-19 116 #define MCFQSPI_CS3 22
5a4acf3e Greg Ungerer 2012-09-19 117 #else
04e037aa Steven King 2012-06-05 118 #define MCFQSPI_CS0 15
04e037aa Steven King 2012-06-05 119 #define MCFQSPI_CS1 16
04e037aa Steven King 2012-06-05 120 #define MCFQSPI_CS2 24
04e037aa Steven King 2012-06-05 121 #define MCFQSPI_CS3 28
5a4acf3e Greg Ungerer 2012-09-19 122 #endif
04e037aa Steven King 2012-06-05 123
04e037aa Steven King 2012-06-05 124 /*
04e037aa Steven King 2012-06-05 125 * I2C module.
04e037aa Steven King 2012-06-05 126 */
86a8280a Andrea Gelmini 2016-05-21 127 #define MCFI2C_BASE0
(MCF_MBAR + 0x280) /* Base address I2C0 */
04e037aa Steven King 2012-06-05 128 #define MCFI2C_SIZE0 0x20
/* Register set size */
04e037aa Steven King 2012-06-05 129
86a8280a Andrea Gelmini 2016-05-21 130 #define MCFI2C_BASE1
(MCF_MBAR2 + 0x440) /* Base address I2C1 */
04e037aa Steven King 2012-06-05 131 #define MCFI2C_SIZE1 0x20
/* Register set size */
5a4acf3e Greg Ungerer 2012-09-19 132
04e037aa Steven King 2012-06-05 133 /*
04e037aa Steven King 2012-06-05 134 * DMA unit base addresses.
04e037aa Steven King 2012-06-05 135 */
04e037aa Steven King 2012-06-05 136 #define MCFDMA_BASE0
(MCF_MBAR + 0x300) /* Base address DMA 0 */
04e037aa Steven King 2012-06-05 137 #define MCFDMA_BASE1
(MCF_MBAR + 0x340) /* Base address DMA 1 */
04e037aa Steven King 2012-06-05 138 #define MCFDMA_BASE2
(MCF_MBAR + 0x380) /* Base address DMA 2 */
04e037aa Steven King 2012-06-05 139 #define MCFDMA_BASE3
(MCF_MBAR + 0x3C0) /* Base address DMA 3 */
04e037aa Steven King 2012-06-05 140
04e037aa Steven King 2012-06-05 141 /*
04e037aa Steven King 2012-06-05 142 * Some symbol defines for the
above...
04e037aa Steven King 2012-06-05 143 */
04e037aa Steven King 2012-06-05 144 #define MCFSIM_SWDICR
MCFSIM_ICR0 /* Watchdog timer ICR */
04e037aa Steven King 2012-06-05 145 #define MCFSIM_TIMER1ICR
MCFSIM_ICR1 /* Timer 1 ICR */
04e037aa Steven King 2012-06-05 146 #define MCFSIM_TIMER2ICR
MCFSIM_ICR2 /* Timer 2 ICR */
04e037aa Steven King 2012-06-05 147 #define MCFSIM_I2CICR
MCFSIM_ICR3 /* I2C ICR */
04e037aa Steven King 2012-06-05 @148 #define MCFSIM_UART1ICR
MCFSIM_ICR4 /* UART 1 ICR */
04e037aa Steven King 2012-06-05 @149 #define MCFSIM_UART2ICR
MCFSIM_ICR5 /* UART 2 ICR */
04e037aa Steven King 2012-06-05 150 #define MCFSIM_DMA0ICR
MCFSIM_ICR6 /* DMA 0 ICR */
04e037aa Steven King 2012-06-05 151 #define MCFSIM_DMA1ICR
MCFSIM_ICR7 /* DMA 1 ICR */
04e037aa Steven King 2012-06-05 152 #define MCFSIM_DMA2ICR
MCFSIM_ICR8 /* DMA 2 ICR */
04e037aa Steven King 2012-06-05 153 #define MCFSIM_DMA3ICR
MCFSIM_ICR9 /* DMA 3 ICR */
04e037aa Steven King 2012-06-05 154 #define MCFSIM_QSPIICR
MCFSIM_ICR10 /* QSPI ICR */
04e037aa Steven King 2012-06-05 155
04e037aa Steven King 2012-06-05 156 /*
04e037aa Steven King 2012-06-05 157 * Define system peripheral IRQ
usage.
04e037aa Steven King 2012-06-05 158 */
04e037aa Steven King 2012-06-05 159 #define MCF_IRQ_QSPI 28
/* QSPI, Level 4 */
04e037aa Steven King 2012-06-05 160 #define MCF_IRQ_I2C0 29
04e037aa Steven King 2012-06-05 161 #define MCF_IRQ_TIMER 30
/* Timer0, Level 6 */
04e037aa Steven King 2012-06-05 162 #define MCF_IRQ_PROFILER 31
/* Timer1, Level 7 */
04e037aa Steven King 2012-06-05 163
04e037aa Steven King 2012-06-05 164 #define MCF_IRQ_UART0 73
/* UART0 */
04e037aa Steven King 2012-06-05 165 #define MCF_IRQ_UART1 74
/* UART1 */
04e037aa Steven King 2012-06-05 166
04e037aa Steven King 2012-06-05 167 /*
04e037aa Steven King 2012-06-05 168 * Define the base interrupt for the
second interrupt controller.
04e037aa Steven King 2012-06-05 169 * We set it to 128, out of the way of
the base interrupts, and plenty
04e037aa Steven King 2012-06-05 170 * of room for its 64 interrupts.
04e037aa Steven King 2012-06-05 171 */
04e037aa Steven King 2012-06-05 172 #define MCFINTC2_VECBASE 128
04e037aa Steven King 2012-06-05 173
04e037aa Steven King 2012-06-05 174 #define MCF_IRQ_GPIO0
(MCFINTC2_VECBASE + 32)
04e037aa Steven King 2012-06-05 175 #define MCF_IRQ_GPIO1
(MCFINTC2_VECBASE + 33)
04e037aa Steven King 2012-06-05 176 #define MCF_IRQ_GPIO2
(MCFINTC2_VECBASE + 34)
04e037aa Steven King 2012-06-05 177 #define MCF_IRQ_GPIO3
(MCFINTC2_VECBASE + 35)
04e037aa Steven King 2012-06-05 178 #define MCF_IRQ_GPIO4
(MCFINTC2_VECBASE + 36)
04e037aa Steven King 2012-06-05 179 #define MCF_IRQ_GPIO5
(MCFINTC2_VECBASE + 37)
04e037aa Steven King 2012-06-05 180 #define MCF_IRQ_GPIO6
(MCFINTC2_VECBASE + 38)
5a4acf3e Greg Ungerer 2012-09-19 181 #define MCF_IRQ_GPIO7
(MCFINTC2_VECBASE + 39)
04e037aa Steven King 2012-06-05 182
04e037aa Steven King 2012-06-05 183 #define MCF_IRQ_USBWUP
(MCFINTC2_VECBASE + 40)
04e037aa Steven King 2012-06-05 184 #define MCF_IRQ_I2C1
(MCFINTC2_VECBASE + 62)
04e037aa Steven King 2012-06-05 185
04e037aa Steven King 2012-06-05 186 /*
04e037aa Steven King 2012-06-05 187 * General purpose IO registers
(in MBAR2).
04e037aa Steven King 2012-06-05 188 */
04e037aa Steven King 2012-06-05 189 #define MCFSIM2_GPIOREAD
(MCF_MBAR2 + 0x000) /* GPIO read values */
04e037aa Steven King 2012-06-05 190 #define MCFSIM2_GPIOWRITE
(MCF_MBAR2 + 0x004) /* GPIO write values */
04e037aa Steven King 2012-06-05 191 #define MCFSIM2_GPIOENABLE
(MCF_MBAR2 + 0x008) /* GPIO enabled */
04e037aa Steven King 2012-06-05 192 #define MCFSIM2_GPIOFUNC
(MCF_MBAR2 + 0x00C) /* GPIO function */
04e037aa Steven King 2012-06-05 193 #define MCFSIM2_GPIO1READ
(MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
04e037aa Steven King 2012-06-05 194 #define MCFSIM2_GPIO1WRITE
(MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
04e037aa Steven King 2012-06-05 195 #define MCFSIM2_GPIO1ENABLE
(MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
04e037aa Steven King 2012-06-05 196 #define MCFSIM2_GPIO1FUNC
(MCF_MBAR2 + 0x0BC) /* GPIO1 function */
04e037aa Steven King 2012-06-05 197
04e037aa Steven King 2012-06-05 198 #define MCFSIM2_GPIOINTSTAT
(MCF_MBAR2 + 0xc0) /* GPIO intr status */
04e037aa Steven King 2012-06-05 199 #define MCFSIM2_GPIOINTCLEAR
(MCF_MBAR2 + 0xc0) /* GPIO intr clear */
04e037aa Steven King 2012-06-05 @200 #define MCFSIM2_GPIOINTENABLE
(MCF_MBAR2 + 0xc4) /* GPIO intr enable */
04e037aa Steven King 2012-06-05 201
:::::: The code at line 200 was first introduced by commit
:::::: 04e037aa4e5f71d11c004e844339d385a89733f6 m68knommu: Add support for the
Coldfire 5251/5253
:::::: TO: Steven King <sfk...@fdwdc.com>
:::::: CC: Greg Ungerer <g...@uclinux.org>
---
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