Re: [PATCH v8 2/3] dmaengine: fsl-edma: add edma version and configurable registers
On 03.08.2018 21:32, Angelo Dureghello wrote:
> This patch adds configurable registers (using __iomem addresses)
> to allow the use of fsl-edma-common code with slightly different
> edma module versions, as Vybrid (v1) and ColdFire (v2) are.
>
> Removal of old membase-referenced registers, amd some fixes on
> macroes are included.
s/amd/and
s/macroes/macros
Also split the macro fixes into a separate commit. We really want one
commit for each change... Its better to have 9 patches which might even
touch the same macros again, but patches which do one logical step.
--
Stefan
>
> Signed-off-by: Angelo Dureghello
> ---
> Changes from v7:
> - patch rewritten from scratch, this patch (2/3) has just been added.
> ---
> drivers/dma/fsl-edma-common.c | 138 ++
> drivers/dma/fsl-edma-common.h | 115 ++--
> drivers/dma/fsl-edma.c| 32
> 3 files changed, 182 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index 0ae7094f477a..948a3ee51bbb 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -9,6 +9,38 @@
>
> #include "fsl-edma-common.h"
>
> +#define EDMA_CR 0x00
> +#define EDMA_ES 0x04
> +#define EDMA_ERQ 0x0C
> +#define EDMA_EEI 0x14
> +#define EDMA_SERQ0x1B
> +#define EDMA_CERQ0x1A
> +#define EDMA_SEEI0x19
> +#define EDMA_CEEI0x18
> +#define EDMA_CINT0x1F
> +#define EDMA_CERR0x1E
> +#define EDMA_SSRT0x1D
> +#define EDMA_CDNE0x1C
> +#define EDMA_INTR0x24
> +#define EDMA_ERR 0x2C
> +
> +#define EDMA64_ERQH 0x08
> +#define EDMA64_EEIH 0x10
> +#define EDMA64_SERQ 0x18
> +#define EDMA64_CERQ 0x19
> +#define EDMA64_SEEI 0x1a
> +#define EDMA64_CEEI 0x1b
> +#define EDMA64_CINT 0x1c
> +#define EDMA64_CERR 0x1d
> +#define EDMA64_SSRT 0x1e
> +#define EDMA64_CDNE 0x1f
> +#define EDMA64_INTH 0x20
> +#define EDMA64_INTL 0x24
> +#define EDMA64_ERRH 0x28
> +#define EDMA64_ERRL 0x2c
> +
> +#define EDMA_TCD 0x1000
> +
> /*
> * R/W functions for big- or little-endian registers:
> * The eDMA controller's endian is independent of the CPU core's endian.
> @@ -67,20 +99,20 @@ EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
>
> static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
> {
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
> - edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
> + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
> + edma_writeb(fsl_chan->edma, ch, regs->serq);
> }
>
> void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
> {
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> - edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
> - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
> + edma_writeb(fsl_chan->edma, ch, regs->cerq);
> + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
> }
> EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
>
> @@ -208,7 +240,7 @@ static size_t fsl_edma_desc_residue(struct
> fsl_edma_chan *fsl_chan,
> struct virt_dma_desc *vdesc, bool in_progress)
> {
> struct fsl_edma_desc *edesc = fsl_chan->edesc;
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
> enum dma_transfer_direction dir = fsl_chan->fsc.dir;
> dma_addr_t cur_addr, dma_addr;
> @@ -224,11 +256,9 @@ static size_t fsl_edma_desc_residue(struct
> fsl_edma_chan *fsl_chan,
> return len;
>
> if (dir == DMA_MEM_TO_DEV)
> - cur_addr = edma_readl(
> - fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
> + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
> else
> - cur_addr = edma_readl(
> - fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
> + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
>
> /* figure out the finished and calculate the residue */
> for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
> @@ -285,7 +315,7 @@ static void fsl_edma_set_tcd_regs(struct
> fsl_edma_chan *fsl_chan,
> struct fsl_edma_hw_tcd *tcd)
> {
> struct fsl_edma_engine *edma = fsl_chan->edma;
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs =
Re: [PATCH v8 2/3] dmaengine: fsl-edma: add edma version and configurable registers
Hi Krzysztof,
many thanks for testing.
On Mon, Aug 06, 2018 at 09:59:35AM +0200, Krzysztof Kozlowski wrote:
> On 3 August 2018 at 21:32, Angelo Dureghello wrote:
> > This patch adds configurable registers (using __iomem addresses)
> > to allow the use of fsl-edma-common code with slightly different
> > edma module versions, as Vybrid (v1) and ColdFire (v2) are.
> >
> > Removal of old membase-referenced registers, amd some fixes on
> > macroes are included.
> >
> > Signed-off-by: Angelo Dureghello
> > ---
> > Changes from v7:
> > - patch rewritten from scratch, this patch (2/3) has just been added.
> > ---
> > drivers/dma/fsl-edma-common.c | 138 ++
> > drivers/dma/fsl-edma-common.h | 115 ++--
> > drivers/dma/fsl-edma.c| 32
> > 3 files changed, 182 insertions(+), 103 deletions(-)
> >
> > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> > index 0ae7094f477a..948a3ee51bbb 100644
> > --- a/drivers/dma/fsl-edma-common.c
> > +++ b/drivers/dma/fsl-edma-common.c
> > @@ -9,6 +9,38 @@
> >
> > #include "fsl-edma-common.h"
> >
> > +#define EDMA_CR0x00
> > +#define EDMA_ES0x04
> > +#define EDMA_ERQ 0x0C
> > +#define EDMA_EEI 0x14
> > +#define EDMA_SERQ 0x1B
> > +#define EDMA_CERQ 0x1A
> > +#define EDMA_SEEI 0x19
> > +#define EDMA_CEEI 0x18
> > +#define EDMA_CINT 0x1F
> > +#define EDMA_CERR 0x1E
> > +#define EDMA_SSRT 0x1D
> > +#define EDMA_CDNE 0x1C
> > +#define EDMA_INTR 0x24
> > +#define EDMA_ERR 0x2C
> > +
> > +#define EDMA64_ERQH0x08
> > +#define EDMA64_EEIH0x10
> > +#define EDMA64_SERQ0x18
> > +#define EDMA64_CERQ0x19
> > +#define EDMA64_SEEI0x1a
> > +#define EDMA64_CEEI0x1b
> > +#define EDMA64_CINT0x1c
> > +#define EDMA64_CERR0x1d
> > +#define EDMA64_SSRT0x1e
> > +#define EDMA64_CDNE0x1f
> > +#define EDMA64_INTH0x20
> > +#define EDMA64_INTL0x24
> > +#define EDMA64_ERRH0x28
> > +#define EDMA64_ERRL0x2c
> > +
> > +#define EDMA_TCD 0x1000
> > +
> > /*
> > * R/W functions for big- or little-endian registers:
> > * The eDMA controller's endian is independent of the CPU core's endian.
> > @@ -67,20 +99,20 @@ EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
> >
> > static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
> > {
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> >
> > - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
> > - edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
> > + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
> > + edma_writeb(fsl_chan->edma, ch, regs->serq);
> > }
> >
> > void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
> > {
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> >
> > - edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
> > - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
> > + edma_writeb(fsl_chan->edma, ch, regs->cerq);
> > + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
> > }
> > EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
> >
> > @@ -208,7 +240,7 @@ static size_t fsl_edma_desc_residue(struct
> > fsl_edma_chan *fsl_chan,
> > struct virt_dma_desc *vdesc, bool in_progress)
> > {
> > struct fsl_edma_desc *edesc = fsl_chan->edesc;
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> > enum dma_transfer_direction dir = fsl_chan->fsc.dir;
> > dma_addr_t cur_addr, dma_addr;
> > @@ -224,11 +256,9 @@ static size_t fsl_edma_desc_residue(struct
> > fsl_edma_chan *fsl_chan,
> > return len;
> >
> > if (dir == DMA_MEM_TO_DEV)
> > - cur_addr = edma_readl(
> > - fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
> > + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
> > else
> > - cur_addr = edma_readl(
> > - fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
> > + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
> >
> > /* figure out the finished and calculate the residue */
> > for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
> > @@ -285,7 +315,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
> > *fsl_chan,
> >
Re: [PATCH v8 2/3] dmaengine: fsl-edma: add edma version and configurable registers
On 3 August 2018 at 21:32, Angelo Dureghello wrote:
> This patch adds configurable registers (using __iomem addresses)
> to allow the use of fsl-edma-common code with slightly different
> edma module versions, as Vybrid (v1) and ColdFire (v2) are.
>
> Removal of old membase-referenced registers, amd some fixes on
> macroes are included.
>
> Signed-off-by: Angelo Dureghello
> ---
> Changes from v7:
> - patch rewritten from scratch, this patch (2/3) has just been added.
> ---
> drivers/dma/fsl-edma-common.c | 138 ++
> drivers/dma/fsl-edma-common.h | 115 ++--
> drivers/dma/fsl-edma.c| 32
> 3 files changed, 182 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index 0ae7094f477a..948a3ee51bbb 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -9,6 +9,38 @@
>
> #include "fsl-edma-common.h"
>
> +#define EDMA_CR0x00
> +#define EDMA_ES0x04
> +#define EDMA_ERQ 0x0C
> +#define EDMA_EEI 0x14
> +#define EDMA_SERQ 0x1B
> +#define EDMA_CERQ 0x1A
> +#define EDMA_SEEI 0x19
> +#define EDMA_CEEI 0x18
> +#define EDMA_CINT 0x1F
> +#define EDMA_CERR 0x1E
> +#define EDMA_SSRT 0x1D
> +#define EDMA_CDNE 0x1C
> +#define EDMA_INTR 0x24
> +#define EDMA_ERR 0x2C
> +
> +#define EDMA64_ERQH0x08
> +#define EDMA64_EEIH0x10
> +#define EDMA64_SERQ0x18
> +#define EDMA64_CERQ0x19
> +#define EDMA64_SEEI0x1a
> +#define EDMA64_CEEI0x1b
> +#define EDMA64_CINT0x1c
> +#define EDMA64_CERR0x1d
> +#define EDMA64_SSRT0x1e
> +#define EDMA64_CDNE0x1f
> +#define EDMA64_INTH0x20
> +#define EDMA64_INTL0x24
> +#define EDMA64_ERRH0x28
> +#define EDMA64_ERRL0x2c
> +
> +#define EDMA_TCD 0x1000
> +
> /*
> * R/W functions for big- or little-endian registers:
> * The eDMA controller's endian is independent of the CPU core's endian.
> @@ -67,20 +99,20 @@ EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
>
> static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
> {
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
> - edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
> + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
> + edma_writeb(fsl_chan->edma, ch, regs->serq);
> }
>
> void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
> {
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> - edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
> - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
> + edma_writeb(fsl_chan->edma, ch, regs->cerq);
> + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
> }
> EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
>
> @@ -208,7 +240,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
> *fsl_chan,
> struct virt_dma_desc *vdesc, bool in_progress)
> {
> struct fsl_edma_desc *edesc = fsl_chan->edesc;
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
> enum dma_transfer_direction dir = fsl_chan->fsc.dir;
> dma_addr_t cur_addr, dma_addr;
> @@ -224,11 +256,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
> *fsl_chan,
> return len;
>
> if (dir == DMA_MEM_TO_DEV)
> - cur_addr = edma_readl(
> - fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
> + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
> else
> - cur_addr = edma_readl(
> - fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
> + cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
>
> /* figure out the finished and calculate the residue */
> for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
> @@ -285,7 +315,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
> *fsl_chan,
> struct fsl_edma_hw_tcd *tcd)
> {
> struct fsl_edma_engine *edma = fsl_chan->edma;
> - void __iomem *addr = fsl_chan->edma->membase;
> + struct edma_regs *regs = _chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> /*
> @@ -293,24 +323,24 @@ static void
