> + }
> +
> + if (chip->reset_gpio) {
> + /* bring chip out of reset */
> + dev_info(>dev, "releasing reset\n");
> + gpiod_set_value(chip->reset_gpio, 0);
>
The pin is already in
the other displays of the family.
'pixelclk-active = 1' is the correct setting for this display!
Thanks, Shawn for the reminder.
Lothar Waßmann
--
___
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0
Hi,
Laurent Pinchart wrote:
Hi Lothar,
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations
and thus should determine
the value of sig_cfg.clk_pol and POL_DE should determine the value of
sig_cfg.enable_pol.
Lothar Waßmann
--
___
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Hi,
Laurent Pinchart wrote:
Hi Lothar,
On Tuesday 18 March 2014 08:50:30 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17
edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or
low) defines the window in which the pixel data is valid.
The flag defines whether data is valid during the HIGH or LOW period of
DE.
Lothar Waßmann
--
___
Ka-Ro
;
+ V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_RGB666;
break;
default:
dev_err(ldb-dev, unable to config di%d panel format\n,
Without this patch Red/Blue on an 18bit LVDS display will be swapped.
Lothar Waßmann
--
___
Ka-Ro
