Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan
clock and set the correct parent.
before:
cat clk_orphan_summary
enable prepare protect
clock count count count rate
accuracy phase
----------------------------------------------------------------------------------------
mipi_dphy_post_div 1 1 0 0
0 0
mipi_dphy_root_clk 1 1 0 0
0 0
cat clk_dump | grep mipi_dphy
mipi_dphy_post_div 1 1 0 0
0 0
mipi_dphy_root_clk 1 1 0 0
0 0
after:
cat clk_dump | grep mipi_dphy
mipi_dphy_src 1 1 0 24000000 0 0
mipi_dphy_cg 1 1 0 24000000 0 0
mipi_dphy_pre_div 1 1 0 24000000 0 0
mipi_dphy_post_div 1 1 0 24000000 0 0
mipi_dphy_root_clk 1 1 0 24000000 0 0
Signed-off-by: Rui Miguel Silva <rui.si...@linaro.org>
Signed-off-by: Rui Miguel Silva <rui.si...@linaro.org>
---
drivers/clk/imx/clk-imx7d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d3cc94..f7f4db2e6fa6 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -729,7 +729,7 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] =
imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300,
0, 6);
clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div",
"mipi_dsi_pre_div", base + 0xa380, 0, 6);
clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div",
"mipi_csi_pre_div", base + 0xa400, 0, 6);
- clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div",
"mipi_csi_dphy_div", base + 0xa480, 0, 6);
+ clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div",
"mipi_dphy_pre_div", base + 0xa480, 0, 6);
clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div",
"sai1_pre_div", base + 0xa500, 0, 6);
clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div",
"sai2_pre_div", base + 0xa580, 0, 6);
clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div",
"sai3_pre_div", base + 0xa600, 0, 6);
--
2.17.0
