On 08/24/2015 11:30 PM, Hans Verkuil wrote:
A quick follow-up to Thierry's excellent review:
On 08/25/2015 02:26 AM, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
snip
+static void
+__tegra_channel_try_format(struct
On Tue, Aug 25, 2015 at 04:15:58PM +0200, Hans Verkuil wrote:
On 08/25/15 15:44, Thierry Reding wrote:
On Mon, Aug 24, 2015 at 05:26:20PM -0700, Bryan Wu wrote:
[...]
For CMA we need increase the default memory size.
I'd rather not rely on CMA at all, especially since we do have a way
On 08/25/15 15:44, Thierry Reding wrote:
On Mon, Aug 24, 2015 at 05:26:20PM -0700, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
+{
+ if (chan-bypass)
+ return;
I don't see this being set anywhere. Is it
On Tue, Aug 25, 2015 at 08:30:41AM +0200, Hans Verkuil wrote:
A quick follow-up to Thierry's excellent review:
On 08/25/2015 02:26 AM, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
snip
+static void
A quick follow-up to Thierry's excellent review:
On 08/25/2015 02:26 AM, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
snip
+static void
+__tegra_channel_try_format(struct tegra_channel *chan, struct
v4l2_pix_format
On 08/25/2015 06:44 AM, Thierry Reding wrote:
On Mon, Aug 24, 2015 at 05:26:20PM -0700, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
[...]
+{
+ if (chan-bypass)
+ return;
I don't see this being
On Mon, Aug 24, 2015 at 05:26:20PM -0700, Bryan Wu wrote:
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
[...]
+#define TEGRA_CSI_PHY_CIL_COMMAND 0x0908
This doesn't seem to be used at all.
Actually this PHY register
On 08/21/2015 02:28 AM, Hans Verkuil wrote:
Hi Bryan,
Thanks for contributing this driver, very much appreciated.
I do have some comments below, basically about the same things we discussed
privately before.
On 08/21/2015 02:51 AM, Bryan Wu wrote:
NVIDIA Tegra processor contains a powerful
On 08/21/2015 06:03 AM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can support up to 6 MIPI CSI camera sensors.
This patch adds a V4L2 media controller and capture driver
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can support up to 6 MIPI CSI camera sensors.
This patch adds a V4L2 media controller and capture driver to support
Tegra VI hardware. It's verified
On 08/21/2015 03:03 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 05:51:39PM -0700, Bryan Wu wrote:
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can support up to 6 MIPI CSI camera sensors.
This patch adds a V4L2 media controller and capture driver
Hi Bryan,
Thanks for contributing this driver, very much appreciated.
I do have some comments below, basically about the same things we discussed
privately before.
On 08/21/2015 02:51 AM, Bryan Wu wrote:
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can support up to 6 MIPI CSI camera sensors.
This patch adds a V4L2 media controller and capture driver to support
Tegra VI hardware. It's verified with Tegra built-in test pattern
generator.
Signed-off-by:
NVIDIA Tegra processor contains a powerful Video Input (VI) hardware
controller which can support up to 6 MIPI CSI camera sensors.
This patch adds a V4L2 media controller and capture driver to support
Tegra VI hardware. It's verified with Tegra built-in test pattern
generator.
Signed-off-by:
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