Ralf Baechle r...@linux-mips.org writes:
16K is a silver bullet solution to all cache aliasing problems. So if
your issue persists with 16K page size, it's not a cache aliasing issue.
Aside there are generally performance gains from the bigger page size.
I wonder why isn't the issue present
On Wed, Oct 09, 2013 at 08:53:20AM +0200, Krzysztof Hałasa wrote:
16K is a silver bullet solution to all cache aliasing problems. So if
your issue persists with 16K page size, it's not a cache aliasing issue.
Aside there are generally performance gains from the bigger page size.
I
Ralf Baechle r...@linux-mips.org writes:
The kernel is supposed to perform the necessary cache flushing, so any
remaining aliasing issue would be considered a bug. But the code is
performance sensitive, some of the problem cases are twisted and complex
so bugs and unsolved corner cases show
Ralf Baechle r...@linux-mips.org writes:
That's fine. You just need to ensure that there are no virtual
aliases.
Does this include virtual aliasing between a 4 KB TLB-mapped page and
a kseg0 address? I don't really have two TLBs pointing to the same page.
One way to do so is to increase the
Ralf Baechle r...@linux-mips.org writes:
That's fine. You just need to ensure that there are no virtual aliases.
One way to do so is to increase the page size to 16kB.
Checked, this thing works fine with 16 KB pages.
--
Krzysztof Halasa
Research Institute for Automation and Measurements
On Tue, Oct 08, 2013 at 10:24:13AM +0200, Krzysztof Hałasa wrote:
That's fine. You just need to ensure that there are no virtual
aliases.
Does this include virtual aliasing between a 4 KB TLB-mapped page and
a kseg0 address? I don't really have two TLBs pointing to the same page.
Yes.
Please forgive me my MIPS TLB ignorance.
It seems there is a TLB entry pointing to the userspace buffer at the
time the kernel pointer (kseg0) is used. Is is an allowed situation on
MIPS 24K?
buffer: len 0x1000 (first page),
userspace pointer 0x77327000,
kernel pointer 0x867ac000
On Mon, Oct 07, 2013 at 10:38:49AM +0200, Krzysztof Hałasa wrote:
Please forgive me my MIPS TLB ignorance.
May the manual be with you :-)
It seems there is a TLB entry pointing to the userspace buffer at the
time the kernel pointer (kseg0) is used. Is is an allowed situation on
MIPS 24K?
I'm debugging a problem with a SOLO6110-based H.264 PCI video encoder on
Atheros AR7100-based (MIPS, big-endian) platform.
BTW this CPU obviously has VIPT data cache, this means a physical page
with multiple virtual addresses (e.g. mapped multiple times) may and
will be cached multiple times.
Hi,
I'm debugging a problem with a SOLO6110-based H.264 PCI video encoder on
Atheros AR7100-based (MIPS, big-endian) platform.
The problem manifests itself with stale data being returned by the
driver (using ioctl VIDIOC_DQBUF). The stale date always starts and ends
on 32-byte cache line
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