Re: VPU on iMX51 babbage board
On 11/12/2014 15:03, Philipp Zabel wrote:
Am Mittwoch, den 10.12.2014, 22:04 -0200 schrieb Fabio Estevam:
On Wed, Dec 10, 2014 at 7:54 PM, Pierluigi Passaro
pierluigi.pass...@phoenixsoftware.it wrote:
Hi all,
I'm trying to use VPU code driver on iMX51 with kernel 3.18, following these
steps:
- disabled DVI interface
- enabled LCD interface
- configured and enabled VPU
- copied iMX51 vpu firmware without header and renamed
v4l-coda7541-imx53.bin in /lib/firmware
Attached you can find the patch and the defconfig I used.
The boot process hangs after loading the firmware at the first attempt of
writing in VPU address space in the function coda_write of file
driver/media/platform/coda/coda-common.c
Is there anything preventing the coda driver to work with iMX51?
Could anyone provide any suggestion on how investigate the problem?
I have only tested the coda driver on mx6, but looking at the
mx51.dtsi you would need this:
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -121,6 +121,7 @@
iram: iram@1ffe {
compatible = mmio-sram;
reg = 0x1ffe 0x2;
+clocks = clks IMX5_CLK_OCRAM;
};
ipu: ipu@4000 {
@@ -584,6 +585,18 @@
clock-names = ipg, ahb, ptp;
status = disabled;
};
+
+vpu: vpu@83ff4000 {
+compatible = fsl,imx53-vpu;
This should be fsl,imx51-vpu, and add a cnm,codahx14.
According to the old imx-vpu-lib code and the vpu_fw_imx51.bin firmware
file, the i.MX51 has a CodaHx14 (0xF00A) as opposed to the i.MX53's
Coda7541 (0xF012).
Thanks for the hint, I'm now going through the old imx-vpu-lib to
understand the CodaHX14 behaviour.
In old imx-vpu-lib, file vpu_util.c, there is a comment that make me
doubtful: i.MX51 has no secondary AXI memory, but use on chip RAM.
As far as I understood, the portion of coda driver affected from this
comment should be around the function coda_setup_iram in coda-bit.c.
How am I supposed to manage this information?
Have I to avoid to use iram for iMX51 (and return on !dev-iram.vaddr)
or go through the function without managing any CodaHX14 specific behaviour?
+reg = 0x83ff4000 0x1000;
+interrupts = 9;
+clocks = clks IMX5_CLK_VPU_REFERENCE_GATE,
+ clks IMX5_CLK_VPU_GATE;
+clock-names = per, ahb;
+resets = src 1;
+iram = iram;
+};
};
+
};
};
Also, not sure if all the required coda patches are available in
3.18, so I tried it on linux-next 20141210 on a imx51-babbage (I had
to disable USB, otherwise linux-next will hang on this board):
[1.368454] coda 83ff4000.vpu: Initialized CODA7541.
[1.373572] coda 83ff4000.vpu: Firmware version: 1.4.50
[1.396695] coda 83ff4000.vpu: codec registered as /dev/video[0-3]
Also, no sure if we need to distinguish mx51 versus mx53 in the coda driver.
Adding Philipp in case he can comment.
Yes, the i.MX51 and i.MX53 firmware files are different. So at least an
entry for i.MX51 with the correct firmware file name has to be added.
regards
Philipp
Thanks
Regards
Pierluigi
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VPU on iMX51 babbage board
Hi all,
I'm trying to use VPU code driver on iMX51 with kernel 3.18, following
these steps:
- disabled DVI interface
- enabled LCD interface
- configured and enabled VPU
- copied iMX51 vpu firmware without header and renamed
v4l-coda7541-imx53.bin in /lib/firmware
Attached you can find the patch and the defconfig I used.
The boot process hangs after loading the firmware at the first attempt
of writing in VPU address space in the function coda_write of file
driver/media/platform/coda/coda-common.c
Is there anything preventing the coda driver to work with iMX51?
Could anyone provide any suggestion on how investigate the problem?
Thanks
Regards
Pierluigi
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 56569ce..e8b372b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -44,6 +44,7 @@
interface-pix-fmt = rgb24;
pinctrl-names = default;
pinctrl-0 = pinctrl_ipu_disp1;
+ status = disabled;
display-timings {
native-mode = timing0;
timing0: dvi {
@@ -71,7 +72,6 @@
interface-pix-fmt = rgb565;
pinctrl-names = default;
pinctrl-0 = pinctrl_ipu_disp2;
- status = disabled;
display-timings {
native-mode = timing1;
timing1: claawvga {
@@ -338,6 +338,10 @@
status = okay;
};
+vpu {
+ status = okay;
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = pinctrl_i2c1;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 92660e1..ce82b1f 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -143,9 +143,17 @@
};
ipu_di1: port@3 {
+#address-cells = 1;
+#size-cells = 0;
reg = 3;
-ipu_di1_disp1: endpoint {
+ipu_di1_disp1: endpoint@0 {
+ reg = 0;
+};
+
+ipu_di1_tve: endpoint@2 {
+ reg = 2;
+ remote-endpoint = tve_in;
};
};
};
@@ -578,6 +586,33 @@
clock-names = ipg, ahb, ptp;
status = disabled;
};
+
+ tve: tve@83ff {
+compatible = fsl,imx53-tve;
+reg = 0x83ff 0x1000;
+interrupts = 92;
+clocks = clks IMX5_CLK_TVE_GATE,
+ clks IMX5_CLK_IPU_DI1_SEL;
+clock-names = tve, di1_sel;
+status = disabled;
+
+port {
+ tve_in: endpoint {
+ remote-endpoint = ipu_di1_tve;
+ };
+};
+ };
+
+ vpu: vpu@83ff4000 {
+compatible = fsl,imx53-vpu;
+reg = 0x83ff4000 0x1000;
+interrupts = 9;
+clocks = clks IMX5_CLK_VPU_REFERENCE_GATE,
+ clks IMX5_CLK_VPU_GATE;
+clock-names = per, ahb;
+resets = src 1;
+iram = iram;
+ };
};
};
};
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_CGROUPS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_MX31LILLY=y
CONFIG_MACH_MX31LITE=y
CONFIG_MACH_PCM037=y
CONFIG_MACH_PCM037_EET=y
CONFIG_MACH_MX31_3DS=y
CONFIG_MACH_MX31MOBOARD=y
CONFIG_MACH_QONG=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_IMX31_DT=y
CONFIG_MACH_IMX35_DT=y
CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_CMDLINE=noinitrd console=ttymxc0,115200
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_BINFMT_MISC=m
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_NETFILTER=y
CONFIG_CAN=y
CONFIG_CAN_FLEXCAN=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
CONFIG_DMA_CMA=y
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
