Re: [PATCH v2 3/9] phy: Add MIPI D-PHY configuration options
Hi! On Mon, Nov 19, 2018 at 03:58:34PM +0200, Sakari Ailus wrote: > > + /** > > +* @clk_pre: > > +* > > +* Time, in nanoseconds, that the HS clock shall be driven by > > +* the transmitter prior to any associated Data Lane beginning > > +* the transition from LP to HS mode. > > +*/ > > + unsigned intclk_pre; > > Is the unit of clk_pre intended to be UI or ns? You're right, it's in UI. > How about adding information on the limits of these values as well? I usually feel like the more you duplicate informations, the higher the chances are to do a mistake and that becomes a burden to maintain over time, but if you feel like it would be best, i'll do it. > > + /** > > +* @lanes: > > +* > > +* Number of lanes used for the transmissions. > > +*/ > > + unsigned char lanes; > > This is related to the data_lanes DT property. I assume this is intended to > be the number of active lanes. And presumably the first "lanes" number of > lanes would be used in that case? I'm not sure I got your question, sorry. But yes, this is the number of active lanes. In the v4l2 world, chances are that this is going to come from the data lanes property, in DRM this is coming from the panel structure. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com signature.asc Description: PGP signature
Re: [PATCH v2 3/9] phy: Add MIPI D-PHY configuration options
Hi Maxime,
On Tue, Nov 06, 2018 at 03:54:15PM +0100, Maxime Ripard wrote:
> Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
> be configured through the generic functions through a custom structure
> added to the generic union.
>
> The parameters added here are the ones defined in the MIPI D-PHY spec, plus
> the number of lanes in use. The current set of parameters should cover all
> the potential users.
>
> Signed-off-by: Maxime Ripard
> ---
> include/linux/phy/phy-mipi-dphy.h | 232 +++-
> include/linux/phy/phy.h | 6 +-
> 2 files changed, 238 insertions(+)
> create mode 100644 include/linux/phy/phy-mipi-dphy.h
>
> diff --git a/include/linux/phy/phy-mipi-dphy.h
> b/include/linux/phy/phy-mipi-dphy.h
> new file mode 100644
> index ..0b05932916af
> --- /dev/null
> +++ b/include/linux/phy/phy-mipi-dphy.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 Cadence Design Systems Inc.
> + */
> +
> +#ifndef __PHY_MIPI_DPHY_H_
> +#define __PHY_MIPI_DPHY_H_
> +
> +#include
> +
> +/**
> + * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
> + *
> + * This structure is used to represent the configuration state of a
> + * MIPI D-PHY phy.
> + */
> +struct phy_configure_opts_mipi_dphy {
> + /**
> + * @clk_miss:
> + *
> + * Timeout, in nanoseconds, for receiver to detect absence of
> + * Clock transitions and disable the Clock Lane HS-RX.
> + */
> + unsigned intclk_miss;
> +
> + /**
> + * @clk_post:
> + *
> + * Time, in nanoseconds, that the transmitter continues to
> + * send HS clock after the last associated Data Lane has
> + * transitioned to LP Mode. Interval is defined as the period
> + * from the end of @hs_trail to the beginning of @clk_trail.
> + */
> + unsigned intclk_post;
> +
> + /**
> + * @clk_pre:
> + *
> + * Time, in nanoseconds, that the HS clock shall be driven by
> + * the transmitter prior to any associated Data Lane beginning
> + * the transition from LP to HS mode.
> + */
> + unsigned intclk_pre;
Is the unit of clk_pre intended to be UI or ns?
How about adding information on the limits of these values as well?
> +
> + /**
> + * @clk_prepare:
> + *
> + * Time, in nanoseconds, that the transmitter drives the Clock
> + * Lane LP-00 Line state immediately before the HS-0 Line
> + * state starting the HS transmission.
> + */
> + unsigned intclk_prepare;
> +
> + /**
> + * @clk_settle:
> + *
> + * Time interval, in nanoseconds, during which the HS receiver
> + * should ignore any Clock Lane HS transitions, starting from
> + * the beginning of @clk_prepare.
> + */
> + unsigned intclk_settle;
> +
> + /**
> + * @clk_term_en:
> + *
> + * Time, in nanoseconds, for the Clock Lane receiver to enable
> + * the HS line termination.
> + */
> + unsigned intclk_term_en;
> +
> + /**
> + * @clk_trail:
> + *
> + * Time, in nanoseconds, that the transmitter drives the HS-0
> + * state after the last payload clock bit of a HS transmission
> + * burst.
> + */
> + unsigned intclk_trail;
> +
> + /**
> + * @clk_zero:
> + *
> + * Time, in nanoseconds, that the transmitter drives the HS-0
> + * state prior to starting the Clock.
> + */
> + unsigned intclk_zero;
> +
> + /**
> + * @d_term_en:
> + *
> + * Time, in nanoseconds, for the Data Lane receiver to enable
> + * the HS line termination.
> + */
> + unsigned intd_term_en;
> +
> + /**
> + * @eot:
> + *
> + * Transmitted time interval, in nanoseconds, from the start
> + * of @hs_trail or @clk_trail, to the start of the LP- 11
> + * state following a HS burst.
> + */
> + unsigned inteot;
> +
> + /**
> + * @hs_exit:
> + *
> + * Time, in nanoseconds, that the transmitter drives LP-11
> + * following a HS burst.
> + */
> + unsigned inths_exit;
> +
> + /**
> + * @hs_prepare:
> + *
> + * Time, in nanoseconds, that the transmitter drives the Data
> + * Lane LP-00 Line state immediately before the HS-0 Line
> + * state starting the HS transmission
> + */
> + unsigned inths_prepare;
> +
> + /**
> + * @hs_settle:
> + *
> + * Time interval, in nanoseconds, during which the HS receiver
> + * shall ignore any Data Lane HS transitions, starting from
> + * the beginning of @hs_prepare.
> + */
> + unsigned inths_settle;
> +
> + /**
> + * @hs_skip:
> + *
> + * Time interval, in nanoseconds, during which the HS-R
[PATCH v2 3/9] phy: Add MIPI D-PHY configuration options
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
be configured through the generic functions through a custom structure
added to the generic union.
The parameters added here are the ones defined in the MIPI D-PHY spec, plus
the number of lanes in use. The current set of parameters should cover all
the potential users.
Signed-off-by: Maxime Ripard
---
include/linux/phy/phy-mipi-dphy.h | 232 +++-
include/linux/phy/phy.h | 6 +-
2 files changed, 238 insertions(+)
create mode 100644 include/linux/phy/phy-mipi-dphy.h
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
new file mode 100644
index ..0b05932916af
--- /dev/null
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_MIPI_DPHY_H_
+#define __PHY_MIPI_DPHY_H_
+
+#include
+
+/**
+ * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * MIPI D-PHY phy.
+ */
+struct phy_configure_opts_mipi_dphy {
+ /**
+* @clk_miss:
+*
+* Timeout, in nanoseconds, for receiver to detect absence of
+* Clock transitions and disable the Clock Lane HS-RX.
+*/
+ unsigned intclk_miss;
+
+ /**
+* @clk_post:
+*
+* Time, in nanoseconds, that the transmitter continues to
+* send HS clock after the last associated Data Lane has
+* transitioned to LP Mode. Interval is defined as the period
+* from the end of @hs_trail to the beginning of @clk_trail.
+*/
+ unsigned intclk_post;
+
+ /**
+* @clk_pre:
+*
+* Time, in nanoseconds, that the HS clock shall be driven by
+* the transmitter prior to any associated Data Lane beginning
+* the transition from LP to HS mode.
+*/
+ unsigned intclk_pre;
+
+ /**
+* @clk_prepare:
+*
+* Time, in nanoseconds, that the transmitter drives the Clock
+* Lane LP-00 Line state immediately before the HS-0 Line
+* state starting the HS transmission.
+*/
+ unsigned intclk_prepare;
+
+ /**
+* @clk_settle:
+*
+* Time interval, in nanoseconds, during which the HS receiver
+* should ignore any Clock Lane HS transitions, starting from
+* the beginning of @clk_prepare.
+*/
+ unsigned intclk_settle;
+
+ /**
+* @clk_term_en:
+*
+* Time, in nanoseconds, for the Clock Lane receiver to enable
+* the HS line termination.
+*/
+ unsigned intclk_term_en;
+
+ /**
+* @clk_trail:
+*
+* Time, in nanoseconds, that the transmitter drives the HS-0
+* state after the last payload clock bit of a HS transmission
+* burst.
+*/
+ unsigned intclk_trail;
+
+ /**
+* @clk_zero:
+*
+* Time, in nanoseconds, that the transmitter drives the HS-0
+* state prior to starting the Clock.
+*/
+ unsigned intclk_zero;
+
+ /**
+* @d_term_en:
+*
+* Time, in nanoseconds, for the Data Lane receiver to enable
+* the HS line termination.
+*/
+ unsigned intd_term_en;
+
+ /**
+* @eot:
+*
+* Transmitted time interval, in nanoseconds, from the start
+* of @hs_trail or @clk_trail, to the start of the LP- 11
+* state following a HS burst.
+*/
+ unsigned inteot;
+
+ /**
+* @hs_exit:
+*
+* Time, in nanoseconds, that the transmitter drives LP-11
+* following a HS burst.
+*/
+ unsigned inths_exit;
+
+ /**
+* @hs_prepare:
+*
+* Time, in nanoseconds, that the transmitter drives the Data
+* Lane LP-00 Line state immediately before the HS-0 Line
+* state starting the HS transmission
+*/
+ unsigned inths_prepare;
+
+ /**
+* @hs_settle:
+*
+* Time interval, in nanoseconds, during which the HS receiver
+* shall ignore any Data Lane HS transitions, starting from
+* the beginning of @hs_prepare.
+*/
+ unsigned inths_settle;
+
+ /**
+* @hs_skip:
+*
+* Time interval, in nanoseconds, during which the HS-RX
+* should ignore any transitions on the Data Lane, following a
+* HS burst. The end point of the interval is defined as the
+* beginning of the LP-11 state following the HS burst.
+*/
+ unsigned inths_skip;
+
+ /**
+* @hs_trail:
+
